Abstract: A testing method and device for detecting the existence of “stuck-open”, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.

Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract: A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.

Abstract: An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.

Abstract: A series of bilingual educational dolls that aid in teaching children additional languages. Each doll has characteristics and costume depicting a specific recognizable Nation and each Nation is represented by both male and female figures. Provided with each doll is an accessory containing an interactive sound transmitting and recording device. Pre-recorded music with educational song lyrics are synchronized with the recording mechanism and are sung in the American English language then immediately repeated in a second language corresponding to the Nation being depicted by the characteristics and costume of doll.

Abstract: A two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well.