Abstract: A computer system has a central processing unit and a functional memory coupled to the central processing unit's memory access circuitry. The functional memory includes random access memory circuitry connected in parallel with field programmable gate array circuitry. The field programmable gate array circuitry receives configuration data from the central processing unit. The configuration data defines what memory addresses the field programmable gate array circuitry will be responsive to and what computational functions the field programmable gate array circuitry will perform. The field programmable gate array circuitry includes input registers for storing data received from the central processing unit when the central processing unit's memory access circuitry asserts a first set of memory addresses defined by the configuration data and result output circuitry for communicating the results computed by the field programmable gate array circuitry.

Abstract: Fast Table Lookup Apparatus For Reading Memory is disclosed for use in conjunction with a logic bus, a memory device, a microprocessor of the type which provides an output logic signal to the bus comprising the contents of an internal register and which includes apparatus for immediately reading the logic signals on the bus into the internal register of the microprocessor, including logic which is external to the microprocessor, for recognizing when the microprocessor provides such a logic signal output and for utilizing the register contents available to address a location within the memory device to cause the substitution of the contents of the memory location within the memory device, which conforms to the microprocessor internal register contents, for the contents of the microprocessor internal register on the bus, and all in sufficient time for the memory location contents to be read into the microprocessor as a part of the next input to the microprocessor.