Abstract: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

Abstract: An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has e an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread.

Abstract: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.

Abstract: The application relates to acquiring images within a 3-dimensional room 4. Image acquiring areas 6 of the at least two imaging units 2 overlap within the room 4 within at least one 3-dimensional overlap box 8. In order to reduce occlusion, there is provided at least one image processing unit 10 arranged for obtaining the acquired images from the at least two imaging units 2, and for determining information about the at least one 3-dimensional overlap box 8, wherein said image processing unit 10 is further arranged for outputting information about the 3-dimensional overlap box 8 for being output by an information output unit 12.

Abstract: A method for determining a relative position of a first camera with respect to a second camera, comprises the followings steps: Determining at least a first, a second and a third position of respective reference points with respect to the first camera, Determining at least a first, a second and a third distance of said respective reference points with respect to the second camera, Calculating the relative position of the second camera with respect to the first camera using at least the first to the third positions and the first to the third distances.

Abstract: A SIMD processor architecture comprises a Linear Processor Array (LPA) (41) having a plurality of Processing Elements (PEs) (42). Each PE (42) operates on its pixel data based on a common instruction which is broadcast to all PEs (42) from a global control processor (44). To enhance the processor's capability in handling de-interlacing algorithms, there is provided a field access module (FAM) (47), an input line memory (48), and a shadow memory (49) within a working line memory (43). The input line memory (48) comprises a previous video field memory (481) for storing a first plurality of pixels from a previous video field, a current video field memory (482) for storing a plurality of pixels from a current video field and a next video field memory (483) for storing a plurality of pixels from a next video field. In a similar manner, the shadow memory (49) comprises a previous-copy video field memory (491), a current-copy video field memory (492), and a next-copy video field memory (493).

Abstract: The invention relates to an integrated image recognition and spectral detection device particularly suitable for monitoring settings of a light. The invention also relates to automatically controlling the settings of a light by image recognition and spectral detection of the light, particularly to automatically controlling the color point of the light in response to the image recognition. The invention provides an integrated image recognition and spectral detection device (10) comprising an image sensor array (12) for recognizing images and motion, and a light filtering structure (14) for detecting spectral components of received light which covers at least a part of the light-sensitive surface of the image sensor array (12). The invention has the main advantage that it combines the recognizing of images and motion with detecting spectral components and, thus, allows to implement a sophisticated automatic control of the settings of a light.

Abstract: A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 . . . 14N), each memory portion being assigned to a particular processing element. A first processing element (PEN) is operable to access a portion of the memory array (14) assigned to that first processing element and also to access a portion of the memory array assigned to a second processing element. Such access is made using an index value indicative of the processing element assigned to the memory position to be accessed.

Abstract: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

Abstract: A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 . . . 14N), each memory portion being assigned to a particular processing element. A first processing element (PEN) is operable to access a portion of the memory array (14) assigned to that first processing element and also to access a portion of the memory array assigned to a second processing element. Such access is made using an index value indicative of the processing element assigned to the memory position to be accessed.

Abstract: A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines of data input to the module (30) serially. Processing can continue in the processor elements (2) in parallel using suitable programming steps.

Abstract: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.

Abstract: A hybrid video encoder which carries out motion estimation and compensation (8) in the transform domain. In such an encoder, the calculation of a prediction block (Ŷ) from previously encoded blocks (Z) stored in the transform-domain frame memory (7) requires a large number of multiplications. This applies particularly to the motion estimation algorithm. In accordance with the invention, only a few DCT coefficients of candidate prediction blocks are calculated, for example, the DC coefficient and some AC coefficients. In a preferred embodiment, the AC coefficients are adaptively selected in dependence upon the motion vector which is being considered. The calculated coefficients of the candidate prediction blocks and the corresponding coefficients of the current input picture block (Y) are then compared to identify the best-matching prediction block.

Abstract: A hybrid video encoder which carries out motion estimation and compensation (8) in the transform domain. In such an encoder, the calculation of a prediction block (Ŷ) from previously encoded blocks (Z) stored in the transform-domain frame memory (7) requires a large number of multiplications. This applies particularly to the motion estimation algorithm. In accordance with the invention, only a few DCT coefficients of candidate prediction blocks are calculated, for example, the DC coefficient and some AC coefficients. In a preferred embodiment, the AC coefficients are adaptively selected in dependence upon the motion vector which is being considered. The calculated coefficients of the candidate prediction blocks and the corresponding coefficients of the current input picture block (Y) are then compared to identify the best-matching prediction block.

Abstract: A method and arrangement is disclosed for creating a high-resolution still picture. A sequence of lower-resolution pictures is subjected to motion-compensated predictive encoding, preferably by an MPEG encoder producing an IPPP. sequence of encoded pictures. The relatively small differences between successive pictures, which are due to motion of the image sensor or motion in the scene, become manifest in motion vectors with sub-pixel accuracy. The high-resolution picture is then created from the decoded pictures and the motion vectors generated by the encoder. The invention is particularly applicable in electronic still picture cameras with a storage medium. The MPEG encoder takes care of data compression, and the decoder also allows playback of the original moving video sequence.

Abstract: A system encodes an input video signal by subjecting the input video signal to noise reduction to obtain a noise-reduced signal, and encoding a difference between the noise-reduced signal and a prediction signal to produce an encoded signal. The system then decodes the encoded signal to obtain the prediction signal. In the system, the noise-reduction step comprises arithmetically combining the input video signal with the prediction signal.