Abstract: Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Abstract: Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Abstract: A semiconductor structure having a through semiconductor via (TSV) which includes a semiconductor wafer of a semiconductor material and having a front side and a back side; front end of the line (FEOL) components; an insulative annulus extending from the front side to the back side, the insulative annulus having a center including the semiconductor material such that the semiconductor material in the center of the insulative annulus is recessed from the back side to form a recess; a metal filling the recess; a through silicon via (TSV) extending in a straight line from the metal-filled recess, through the center of the semiconductor material in the center of the insulative annulus and into the FEOL components such that there is semiconductor material between the TSV and the insulative annulus.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: A structure including a substrate having a backside, a first through silicon via having sides, a bottom surface, and a first height protruding from the backside of the substrate, and a first conductor facing the backside of the substrate and in electrical contact with the first through silicon via. The structure further including a second through silicon via having sides, a bottom surface, and a second height protruding from the backside of the substrate, wherein the second height is less than the first height, and a second conductor facing the backside of the substrate and in electrical contact with the second through silicon via, where a first via liner contacts the sides and the bottom surface of the first through silicon via and contacts the bottom surface but not the sides of the second through silicon via.

Abstract: A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal such that the metal is recessed with respect to at least one of the active side and the inactive side and does not entirely fill the TSVs; defining capture pad areas on the at least one of the active side and inactive side adjacent to the recessed TSVs; filling the capture pad areas and recessed TSVs with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. Also disclosed is a semiconductor substrate having a capture pad.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal such that the metal is recessed with respect to at least one of the active side and the inactive side and does not entirely fill the TSVs; defining capture pad areas on the at least one of the active side and inactive side adjacent to the recessed TSVs; filling the capture pad areas and recessed TSVs with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. Also disclosed is a semiconductor substrate having a capture pad.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

Abstract: A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.

Abstract: A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.

Abstract: A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.