Patents by Inventor Richard Paul Volant
Richard Paul Volant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8386977Abstract: A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks.Type: GrantFiled: May 23, 2011Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, William Francis Landers, Kevin S. Petrarca, Richard Paul Volant
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Publication number: 20120304138Abstract: A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, William Francis Landers, Kevin S. Petrarca, Richard Paul Volant
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Patent number: 7855137Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.Type: GrantFiled: August 12, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Waldemar Walter Kocon, Kevin Shawn Petrarca, Richard Paul Volant
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Patent number: 7833893Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.Type: GrantFiled: July 10, 2007Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Stephan Grunow, Kaushik A. Kumar, Kevin Shawn Petrarca, Richard Paul Volant
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Publication number: 20100038777Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Waldemar Walter Kocon, Kevin Shawn Petrarca, Richard Paul Volant
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Publication number: 20090017616Abstract: A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Inventors: Stephan Grunow, Kaushik A. Kumar, Kevin Shawn Petrarca, Richard Paul Volant
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Patent number: 7273804Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.Type: GrantFiled: January 6, 2005Date of Patent: September 25, 2007Assignee: International Business Machines CorporationInventors: David Angell, Frederic Beaulieu, Takashi Hisada, Adreanne Kelly, Samuel Roy McKnight, Hiromitsu Miyai, Kevin Shawn Petrarca, Wolfgang Sauter, Richard Paul Volant, Caitlin W. Weinstein
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Patent number: 6982493Abstract: Disclosed is a wedgebond pad structure which includes a semiconductor substrate and a wedgebond pad. The wedgebond pad has a surface which includes a curved or v-shaped feature for receiving a wedge bond. The curved or v-shaped feature may be raised or recessed with respect to the wedgebond pad surface.Type: GrantFiled: April 3, 2003Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Kevin Shawn Petrarca, Richard Paul Volant
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Patent number: 6864578Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.Type: GrantFiled: April 3, 2003Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: David Angell, Frederic Beaulieu, Takashi Hisada, Adreanne Kelly, Samuel Roy McKnight, Hiromitsu Miyai, Kevin Shawn Petrarca, Wolfgang Sauter, Richard Paul Volant, Caitlin W. Weinstein
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Patent number: 6819000Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.Type: GrantFiled: October 23, 2003Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
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Publication number: 20040195679Abstract: Disclosed is a wedgebond pad structure which includes a semiconductor substrate and a wedgebond pad. The wedgebond pad has a surface which includes a curved or v-shaped feature for receiving a wedge bond. The curved or v-shaped feature may be raised or recessed with respect to the wedgebond pad surface.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Applicant: International Business Machines CorporationInventors: Kevin Shawn Petrarca, Richard Paul Volant
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Publication number: 20040195642Abstract: Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Inventors: David Angell, Frederic Beaulieu, Takashi Hisada, Adreanne Kelly, Samuel Roy McKnight, Hiromitsu Miyai, Kevin Shawn Petrarca, Wolfgang Sauter, Richard Paul Volant, Caitlin W. Weinstein
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Patent number: 6747472Abstract: A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.Type: GrantFiled: January 18, 2002Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J. Van Horn, Richard Paul Volant, George Frederick Walker
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Patent number: 6732908Abstract: A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.Type: GrantFiled: January 18, 2002Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Bruce Kenneth Furman, Maheswaran Surendra, Sherif A. Goma, Simon M. Karecki, John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
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Publication number: 20040084782Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said the device chips are joined to said the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.Type: ApplicationFiled: October 23, 2003Publication date: May 6, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
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Patent number: 6661098Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.Type: GrantFiled: January 18, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
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Publication number: 20030137058Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.Type: ApplicationFiled: January 18, 2002Publication date: July 24, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
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Publication number: 20030136813Abstract: A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.Type: ApplicationFiled: January 18, 2002Publication date: July 24, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J. Van Horn, Richard Paul Volant, George Frederick Walker
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Publication number: 20030136814Abstract: A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.Type: ApplicationFiled: January 18, 2002Publication date: July 24, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Kenneth Furman, Maheswaran Surendra, Sherif A. Goma, Simon M. Karecki, John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker, Anna Karecki
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Patent number: 6413868Abstract: Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.Type: GrantFiled: January 4, 2001Date of Patent: July 2, 2002Assignee: International Business Machines CorporationInventors: Thomas Adam Bartush, David Louis Harame, John Chester Malinowski, Dawn Tudryn Piciacchio, Christopher Lee Tessler, Richard Paul Volant