Abstract: A system for monitoring a person in a building having multiple rooms. The system comprises a wireless sensor system for detecting and collecting movements of the person. The wireless system comprises: a data collecting device with an RF receiver; a plurality of wireless signaling devices with an RF transmitter, an adjustable room setting, a multi-color light source, and a push button; and a computing device with analysis software, and communication means for transmitting analysis date to viewing devices having a color display. When the button is pushed, a specific color is shown, the color is linked to the room-type and is set during configuration. The same color is used in the viewing devices. This allows easy and intuitive configuration, and easy and intuitive interpretation of the analysis data.

Abstract: A system for monitoring a person in a building having multiple rooms. The system comprises a wireless sensor system for detecting and collecting movements of the person. The wireless system comprises: a data collecting device with an RF receiver; a plurality of wireless signaling devices with an RF transmitter, an adjustable room setting, a multi-color light source, and a push button; and a computing device with analysis software, and communication means for transmitting analysis date to viewing devices having a color display. When the button is pushed, a specific color is shown, the color is linked to the room-type and is set during configuration. The same color is used in the viewing devices. This allows easy and intuitive configuration, and easy and intuitive interpretation of the analysis data.

Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

Abstract: A method of calibrating a camera system which is capable of recording at least two images simultaneously is described. The method comprises the step of processing a first pair of images, wherein the processing step comprises transforming at least one of a first and a second image of the first pair through a projective map on a plane, the map depending on one or more parameter values, so as to align an epipolar line in the first image with a corresponding epipolar line in the second image of the first pair, resulting in a second pair of images.

Abstract: The subject matter hereof relates to error detection. Various example embodiments for error defection are disclosed. In an example method of error detection in a Module UnderTest (MUT), a parity signal representing the parity of an MUT output is compared to a parity signal representing the parity of an errorless MUT output. In an example system, an Actual Parity Generator provides a parity signal representing the parity of on MUT output, a State Parity Generator provides a parity signal representing the parity of an errorless MUT output, and a comparator compares these two parity signals.

Abstract: The invention refers to a flash light compensation system and corresponding method for digital camera systems, wherein a luminance compensation is carried out on an image of a scene (3) picked-up by an image sensor (1), on the basis of a respective intensity field measured by a plurality of sensors (4, 5), when the scene is illuminated by flash light emitted by a flash device (2). Depending upon the output signals of the plurality of sensors a depth field of the scene is estimated, and this estimation provides a basis for the luminance adjustment on the scene picked up as an image while illuminated by the flash device. The system and method is suitable for effectively reducing the problem of unevenly distributed lighting on a picked-up image of the scene.

Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

Abstract: The invention refers to a flash light compensation system and corresponding method for digital camera systems, wherein a luminance compensation is carried out on an image of a scene (3) picked-up by an image sensor (1), on the basis of a respective intensity field measured by a plurality of sensors (4, 5), when the scene is illuminated by flash light emitted by a flash device (2). Depending upon the output signals of the plurality of sensors a depth field of the scene is estimated, and this estimation provides a basis for the luminance adjustment on the scene picked up as an image while illuminated by the flash device. The system and method is suitable for effectively reducing the problem of unevenly distributed lighting on a picked-up image of the scene.

Abstract: A method for detecting a pattern in an image comprising a grid of data elements processes each data element in a predetermined order. In processing one of the data elements, the following steps are carried out. It is checked (100) whether a predetermined local feature is present at the data element to generate information about the local feature if it is present. A propagation direction (42) is associated with the generated information, where the propagation direction is chosen such that data elements along the propagation direction still have to be processed. The generated information, as well as the information propagated to the data element, are propagated (110) to respective data elements closest to the data element along the respective propagation directions associated with the respective information.

Abstract: A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element (1) further comprises a storage element (SE) (11), which supports the processing of local customized (i.e. data dependent) processing in the processing element (1), such as lookup table operations and the storing local coefficient data.

Abstract: A method of calibrating a camera system which is capable of recording at least two images simultaneously is described. The method comprises the step of processing a first pair of images, wherein the processing step comprises transforming at least one of a first and a second image of the first pair through a projective map on a plane, the map depending on one or more parameter values, so as to align an epipolar line in the first image with a corresponding epipolar line in the second image of the first pair, resulting in a second pair of images.

Abstract: An image processing apparatus (400) comprises a SIMD processor (401) which scans an image frame for regions of interest (step 301), for example corresponding to regions having objects or lines of interest. Each region of interest is rescanned to an orthogonal grid. The orthogonal grids are then floorplanned so that they are rearranged into a smaller subset of image lines. The floorplanning consists of mapping a set of rectangles into a compressed frame portion. Optionally, the rectangles can be rotated in order to allow the rectangles to be packed more densely. The SIMD processor (401) then processes the floorplanned image data (step 307). Once the image data has been processed by the SIMD processor, the DSP (405) re-associates the processed data (step 309), using information stored during floorplanning. The image processing apparatus results in a more efficient use of the SIMD processor (401).

Abstract: A video processing apparatus comprises a first camera (I) for producing a first image signal (9), and a second camera (3) for producing a second image signal (11). The first image signal (9) and the second image signal (11) are offset versions of the same scene, for example relating to “right” and “left” versions of the scene as viewed through the first and second cameras, respectively. A depth estimator (5) receives the first and second image signals (9, 11), and produces a depth signal (13) for a region in the scene. A data compressor (7) receives an image signal from one of the cameras, for example the first camera (1), and compresses the video data in the image signal to produce a compressed image signal (14). The data compression for a particular region is performed based on the depth signal (13) received from the depth estimator (5) for that region. The apparatus can be configured to compress image data for objects in the foreground with a higher resolution than objects located in the background.

Abstract: The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other.

Abstract: The invention proposes a method of and a device for coding a signal (S) to obtain a scalable bit-stream (O). The signal (S) comprises blocks of values. Each block is represented (20) as a sequence of bit planes and the values are scanned and transmitted (21, 23) in an order of decreasing bit plane significance. For each bit plane the scanning and transmitting (21,23) are performed in a rectangular scan zone (RMAX/CMAX) starting from a corner of the block (usually an upper-left corner). Preferably, the scanning and transmitting (21,23) is performed on each block individually. The produced bit-stream (O) is quantized to a desired bit-rate by simple truncating (3) the bit-stream (O) at a desired position.

Abstract: The invention relates to a digital system (1) and the method for error detection thereof. The digital system (1) comprises, as it's main core, a Module under Test (110) included in a Digital Processing Unit (100) and a State Parity Generator (SPG) (300). The SPG (300) is an equivalent with respect to parity of the Module under Test (300). An equivalent with respect to parity is a combinatorial circuit that, when an imput vector is applied at the imput of both Module under Test (110) and SPG (300), the output of the SPG (300) generates at it's output the parity of the transfer function of the Module under Test (110).

Abstract: Storing of data items in a memory (31) is provided wherein the data items are divided into successive data pieces of decreasing significance, and the data pieces are stored in respective parts of the memory (31), and when applying a data piece to the memory (31) in case all candidate memory parts are assigned to other data pieces: if the significance of the applied data piece is lower than a lowest significance of the other data pieces, discarding the applied data piece; if the significance of the applied data piece is higher than the lowest significance, storing the applied data piece in one of the candidate memory parts at expense of a given other data piece which has a lower significance than the significance of the applied data piece. Advantageous use of the invention is made in applications using a device of fixed storage capacity for storing compressible data, such as video, images, audio, speech.

Abstract: Method and arrangement for encoding a video signal, wherein a selection (39) is made between the generation of a motion-compensated encoded video signal (I, B, P) and the generation of a higher-resolution picture (IH). The creation of the higher-resolution picture (IH) relies on estimating motion in a series of subsequent pictures (f1,2,3, . . . ) of lower resolution. The higher-resolution picture (IH) is interpolated (38) from these pictures (f1,2,3, . . . ). In a preferred embodiment of the invention, previously determined regions of interest (S(ROI)) are selected (36) from the video signal. The pictures relating to these regions of interest (f1,2,3, . . . ) occupy less memory (33) than entire pictures as picked up by an image sensor (2). A conventional picture memory (33) is sufficient to store the series of pictures (f1,2,3, . . . ) that relates to a certain region of interest. Motion estimation (31) is performed on these pictures and their motion vectors (m) are stored in a vector memory (37).

Abstract: Errors are corrected that occur in the operation of a combinatorial logic circuit in an integrated circuit.

Abstract: Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized (3). The memory (5) is organized in corresponding memory layers (501-504). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links (511-513, 521-522) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory. FIG. 2.