Patents by Inventor Richard Pierre Fournel

Richard Pierre Fournel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for programming read-only memory cells and associated memories
    Patent number: 7023060
    Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: April 4, 2006
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Pierre Fournel
  • Methods for programming read-only memory cells and associated memories
    Patent number: 6144078
    Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: November 7, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Pierre Fournel
  • Physical fuse for semiconductor integrated circuit
    Patent number: 5969403
    Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: October 19, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Richard Pierre Fournel, Serge Fruhauf, Fran.cedilla.ois Tailliet
  • Circuit for the detection of voltage thresholds
    Patent number: 5736876
    Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: April 7, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Richard Pierre Fournel
  • Method of irreversibly locking a portion of a semiconductor device
    Patent number: 5665627
    Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 9, 1997
    Assignee: SGS Thomson Microelectronics S.A.
    Inventors: Richard Pierre Fournel, Serge Fruhauf, Fran.cedilla.ois Tailliet
  • Relaxation oscillator using integrated RTC structure
    Patent number: 5661324
    Abstract: A resistor-capacitor-transistor type of integrated circuit comprises mainly a non-self-aligned N diffusion bar 1 covered with a polysilicon plate, and a drain type N diffusion, self-aligned by the polysilicon plate. The resulting structure is a distributed resistor-capacitor-transistor quadripole whose main characteristics are that it is very compact and that the time taken by the capacitor to get discharged through the transistor is independent of the dimensions of the structure.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: August 26, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Richard Pierre Fournel, Fran.cedilla.ois Tailliet