Patents by Inventor Richard Portune

Richard Portune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110201256
    Abstract: A system and method for thermal management of a device under test (DUT). In particular, a system is described for performing optical microscopy. The system includes a heat spreader window that consists of substantially undoped silicon. The window is configured to be coupled to a back side of a substrate of a DUT such that thermal energy from the DUT is spread to the heat spreader window. A contact region is coupled to the heat spreader window. The contact region is configured for contact with a solid immersion lens (SIL) optical system for optical examination of the DUT. A heat exchanger is coupled to the heat spreader window for removing the thermal energy from the DUT during its operation, wherein the heat exchanger is configured to allow access to the heat spreader window.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Inventor: Richard A. PORTUNE
  • Patent number: 7956625
    Abstract: A system and method for thermal management of a device under test (DUT). In particular, a system is described for performing optical microscopy. The system includes a heat spreader window that consists of substantially undoped silicon. The window is configured to be coupled to a back side of a substrate of a DUT such that thermal energy from the DUT is spread to the heat spreader window. A contact region is coupled to the heat spreader window. The contact region is configured for contact with a solid immersion lens (SIL) optical system for optical examination of the DUT. A heat exchanger is coupled to the heat spreader window for removing the thermal energy from the DUT during its operation, wherein the heat exchanger is configured to allow access to the heat spreader window.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: June 7, 2011
    Assignee: DCG Systems, Inc.
    Inventor: Richard A. Portune
  • Patent number: 7314767
    Abstract: A method is provided for preparing a semiconductor wafer for testing. The method includes selecting a die to be tested; measuring a diagonal of the die; thinning an area over the die extending beyond the scribe lines, the thinned area may be a circular area having a diameter that is larger than the measured diagonal; providing an insert inside the thinned area; and providing an adhesive on the peripheral area of the insert so as not to obscure the optical path to the die. The insert is advantageously made of an undoped silicon.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: January 1, 2008
    Assignee: Credence Systems Corporation
    Inventor: Richard A. Portune
  • Publication number: 20070152696
    Abstract: A method for forming an improved electrical connection to a die or wafer which does not utilize micro-probes, is physically compatible with ultra-high NA objectives used for low photon emission observation, forms more secure electrical connections, is practical for contacting a die at any position on a full wafer. The method can be used for failure analysis utilizing electrical stimulation of the die yielding optical or thermal output. It can also be used in methods wherein optical stimulation yields electrical output.
    Type: Application
    Filed: March 21, 2006
    Publication date: July 5, 2007
    Inventors: Larry Ross, Richard Portune
  • Publication number: 20060267009
    Abstract: A method is provided for preparing a semiconductor wafer for testing. The method includes selecting a die to be tested; measuring a diagonal of the die; thinning an area over the die extending beyond the scribe lines, the thinned area may be a circular area having a diameter that is larger than the measured diagonal; providing an insert inside the thinned area; and providing an adhesive on the peripheral area of the insert so as not to obscure the optical path to the die. The insert is advantageously made of an undoped silicon.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Inventor: Richard Portune
  • Patent number: 5966212
    Abstract: A system includes multiple optical Fourier transform cells which simultaneously scan a device under test. The illuminated area for each Fourier transform cell is small to provide high resolution, while the number of cells is large to cover a relatively wide area and keep inspection speed high. The advantages of optical computing performed by Fourier transform optics also keeps the inspection speed high because illuminated areas are large when compared to the resolution and Fourier transforms are linear shift invariant so that optical measurements can be performed during scanning. In one embodiment, Fourier transform cells are offset from each other perpendicular to the scan direction by less that the width of an illuminated area. This provides complete coverage during scanning of a device under test. Because the illumination for the Fourier transform is collimated, the system is insensitive to focusing errors due to fluctuations in working distance.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: October 12, 1999
    Assignee: Pixel Systems, Inc.
    Inventors: Lawrence Hendler, Michael P. C. Watts, Richard A. Portune