Abstract: A pharmaceutical composition, a combination product including the composition and a method of manufacturing the composition. The composition includes a particulate complex of API bound with a crosslinked polysaccharide micro sponge. The combination product includes a dosage form of the particulate complex within a container. The amount of the particulate complex is selected to provide a defined dose of the API. The formulation may be heated within the container by a vaporizer device, vaporizing the API and dissociating the API from the micro sponge as vapour, which passes through apertures in the container facilitating administration of the API by inhalation of the vapour. The apertures are sized to facilitate passage of the vapour but prevent passage the particulate complex. The API may be hydrophobic such as phytocannabinoids or hydrophilic such as nicotine. The pharmaceutical composition may be manufactured by driving binding of the API to the micro sponge in solution.

Abstract: Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.

Abstract: An example apparatus includes a first printed circuit board (PCB) having a power layer, a ground layer, and a slot. The slot includes a first power electrical contact that is electrically connected to the power layer and a first ground electrical contact that is connected to the ground layer. The slot extends orthogonally or obliquely through multiple layers of the first PCB. A second PCB includes a second power electrical contact, a second ground electrical contact, and capacitors electrically connected between the second power electrical contact and the second ground electrical contact. The second PCB is configured for insertion into the slot to form an electrical connection between the first power electrical contact and the second power electrical contact and between the first ground electrical contact and the second ground electrical contact.

Abstract: An example apparatus includes a first printed circuit board (PCB) having a power layer, a ground layer, and a slot. The slot includes a first power electrical contact that is electrically connected to the power layer and a first ground electrical contact that is connected to the ground layer. The slot extends orthogonally or obliquely through multiple layers of the first PCB. A second PCB includes a second power electrical contact, a second ground electrical contact, and capacitors electrically connected between the second power electrical contact and the second ground electrical contact. The second PCB is configured for insertion into the slot to form an electrical connection between the first power electrical contact and the second power electrical contact and between the first ground electrical contact and the second ground electrical contact.

Abstract: An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.

Abstract: Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.

Abstract: An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.

Abstract: Example automatic test equipment (ATE) includes: a test instrument for outputting test signals to test a device under test (DUT), and for receiving response signals based on the test signals; a device interface board (DIB) connected to the test instrument, with the DIB including an application space having a site to which the DUT connects, and with the test signals and the response signals passing through the site; and calibration circuitry in the application space on the DIB. The calibration circuitry includes a communication interface over which communications pass, with the communications comprising control signals to the calibration circuitry and measurement signals from the calibration circuitry. The calibration circuitry also includes non-volatile memory to store calibration data and is controllable, based on the control signals, to pass the test signals from the test instrument to the DUT and to pass the response signals from the DUT to the test instrument.

Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

Abstract: Example automatic test equipment (ATE) includes: a test instrument for outputting test signals to test a device under test (DUT), and for receiving response signals based on the test signals; a device interface board (DIB) connected to the test instrument, with the DIB including an application space having a site to which the DUT connects, and with the test signals and the response signals passing through the site; and calibration circuitry in the application space on the DIB. The calibration circuitry includes a communication interface over which communications pass, with the communications comprising control signals to the calibration circuitry and measurement signals from the calibration circuitry. The calibration circuitry also includes non-volatile memory to store calibration data and is controllable, based on the control signals, to pass the test signals from the test instrument to the DUT and to pass the response signals from the DUT to the test instrument.

Abstract: An example system for testing camera modules may include: a polygonal structure that is rotatable, where the polygonal structure includes faces, each of which is configured to receive at least one camera module under test; and targets facing at least some of the faces of the polygonal structure, where each target is usable in testing a corresponding camera module facing the each target.

Abstract: An example system for testing camera modules may include: a polygonal structure that is rotatable, where the polygonal structure includes faces, each of which is configured to receive at least one camera module under test; and targets facing at least some of the faces of the polygonal structure, where each target is usable in testing a corresponding camera module facing the each target.

Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

Abstract: An automated optical inspection (AOI) system includes component learning integrated with the inspection of a circuit board. The AOI system includes a component learning area that can be viewed by an imaging system used to inspect the circuit board in an inspection area. The component learning area can correspond to a region proximate the inspection area. The automated optical inspection system receives board inspection and component learn requests and determines opportune times to learn new component characteristics during the board inspection process so as to minimize the impact of the learning process on the overall inspection efficiency.

Abstract: In a loop holding mechanism (31), loop engaging pins (39) which are carried by pin blocks (38) are arranged successively to engage at a feed end (310) of the mechanism loop portions of yarns formed at opposite side edges of a multi-axial yarn structure being formed. The pin blocks (38) at each side of the mechanism (31) advance in abutting relationship along an advancement track (32) to a delivery end (311) of the mechanism (31) where they are returned along a return track (34) and again engaged in the successively formed loop portions.

Abstract: A hybrid scanner for switching internal analog buses to system pin channels. Semiconductor switches switch most scanner buses to system pin channels, but mechanical relays perform switching for at least one bus used for high-current test signals. To perform low-impedance guarding and/or high-current backdriving, the low impedance, high current bus is typically connectable to one or more overdriver circuits and a guard voltage potential through mechanical relays. The scanner is capable of supporting in-circuit tests covering the most significant regions of the fault spectrum can be made more reliable and much smaller and less costly than the scanners conventionally used in traditional broad spectrum testers. It turns out that this test-supporting capability can be achieved by adding only a few mechanical relays to an otherwise semiconductor-switch-based scanner. Only those necessary to support low-impedance and high-current test operations.

Abstract: A system for generating programs for a variety of testing stations. A program generator reads a common rule set to generate test instructions for an electrical tester, an optical inspector, and an x-ray inspector. Over time, the system collects defect data that may affect the triggering of certain rules in the rule set.

Abstract: Propagation delays in signal paths leading to respective pins in an array of test system pins are determined using a probe which is wiped across the pins. Timing signals are applied to each of the signal paths in parallel, and pin identifying signals are applied to each of the signal paths such that each signal path and the pin to which it is connected receives a different pin identifying signal. When the probe is wiped across the pins, it detects signals on each of the pins with which it comes into contact. Any pin with which the probe is in contact is identified by detection of the pin identifying signal. The identifying and timing signals alternate, and once a pin has been identified, the timing signals on that pin are detected. The propagation delay in the signal path to the identified pin is then calculated from the detected timing signals.

Abstract: A method and apparatus for sequentially refreshing each of an array of sample and hold output circuits in a DC level generator. Each sample and hold circuit makes a selected DC voltage available. For each of the sample and hold output circuits in turn, the voltage which it is desired to store in that circuit is generated. The generated voltage is compared with the voltage stored by that one sample and hold output circuit to produce a voltage difference signal and an error correction storage and hold circuit is charged to a voltage proportional to the voltage difference signal. Charge proportional to the voltage stored in the error correction storage and hold circuit is then transferred to the selected one sample and hold output circuit to reduce the difference between the compared voltages.