Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Abstract: A system comprising a transceiver and processing logic coupled to the transceiver. The processing logic is configured to determine an activity level of a network associated with the system and, based on the activity level, adjust a frequency with which the processing logic monitors signals broadcast by the network.