Abstract: A client with a processor having at least one core and a client timer, and an ETAP module comprising an ETAP high resolution timer, wherein the client processor is programed to use the ETAP timer instead of the client timer to perform timed attestation and produce test results.

Abstract: A Timed Attestation Process (TAP) utilizes a CPU bus cycle counter/timer to accurately measure the time needed to calculate a specific function value for an attestation query in an embedded system. The attestation query takes into account embedded software and the hardware data path. An attestation value database stores the unique timing and function data associated with each hardware design element in the embedded device, which each have unique timing characteristics. By utilizing the CPU bus cycle counter/timer of the client device, the TAP increases the time accuracy to the smallest tolerance possible relative to a particular CPU (typically +/?one instruction cycle). The integrity of the embedded software contained in the permanent storage elements and the hardware timing to access each component is verifiable against the unique timing characteristics stored in the database. With this timing characteristic, each hardware element is linked to a specific software configuration.