Abstract: A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers.

Abstract: A standard cell array is disclosed having improved device isolation, customized metal routing under power busses, a gate array core cell having improved internal routing channels, and shared power busses. A fake gate is located adjacent a source of drain of a transistor within each cell, and is coupled to a supply voltage for isolating the transistors within each cell. Additional metallization strips partially overlap and extend between adjacent rows and columns, respectively, of the core cells for providing supply voltages thereto. Further metallization strips for conducting signals overlie the internal portion of the core cell and extend the entire length of the row or column of core cells.

Abstract: A method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" (dummy) gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material (refractory metal) is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alternatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub.