Abstract: A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19) mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form memory chip cube. One is a high melting point lead tin alloy (HMA), the other is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over another functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs. The memory cube (42) is formed by joining the memory chip pairs together in a boat (30) with a silicon bar (41) maintaining spacing during manufacture. The memory chip cube (42) as well as the supporting chips are then placed and joined to the packaging substrate.

Abstract: A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground).

Abstract: A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19)mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form the memory chip cube. One is a high melting point lead tin alloy (HMA), another is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over other functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs.

Abstract: A low temperature conduction module comprising a cold plate having recesses around the periphery thereof to accommodate memory cubes is disclosed. The recesses accommodating the memory cubes are of such depth and dimension as to enclose the memory cube on all but one side, thereby greatly enhancing the conduction of the heat generated by the memory cube to the cold plate. The memory cube may be surrounded by a material which possesses excellent thermal conductive properties to insure efficient transfer of the heat from the memory cube to the cold plate. The plurality of memory cubes so positioned within the cold plate may be connected by a flexible cable surrounding the cold plate and having branch conductors extending to connect with computer processors enclosed within the same low temperature conduction module.

Abstract: A gasket is fabricated with electrical flex cables extending through the gasket in order to electrically communicate from the outside of a vacuum chamber with the electrical devices positioned within a vacuum chamber of a cryogenically cooled module. The gasket is fabricated from elastomeric, dielectric materials such as neoprene to effect a seal between the portions of the vacuum chamber and also to seal between the gasket material and the conductors of the flex cables which pass through the gasket.

Abstract: Low voltage, low power transistor driver/receiver and logic circuits are disclosed comprising a pair of NPN transistors, the base of the first transistor being directly connected to an input terminal and, via a resistor, to the base of the second transistor. A third NPN transistor is connected with the second transistor in series circuit across a low voltage power supply. The junction between the series-connected transistors is coupled to an output terminal. A diode is connected between a point on the resistor and the collector of the second transistor to prevent saturation. The emitter of the second transistor is connected through a small or zero resistance to one terminal of the power supply. The down level at the output terminal is held by a transistor or diode clamp connected between the base of the third transistor and the other terminal of the power supply.

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.

Abstract: A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

Abstract: A complementary bipolar transistor circuit characterized by low power dissipation and fast response for driving capacitive loads in response to input logic signals. An emitter follower series-connected pair of complementary transistors provide an output signal at the junction between their commonly connected emitters. The NPN transistor of the pair of transistors is directly driven by an input signal applied to its base. The PNP transistor of the pair of transistors is driven through a second series-connected NPN transistor and Schottky diode, the second NPN transistor base also receiving said input signal. The forward voltage of the Schottky diode is less than the V.sub.be of the PNP transistor. The PNP transistor nominally is held off and conducts only on negative-going input signal transitions to discharge the capacitive load. The NPN transistor of the pair of transitors conducts only on positive-going input signal transitions to charge the capacitive load.

Abstract: A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V.sub.be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other.In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal.

Abstract: A high speed current switch logic circuit wherein a first and a second transistor are operated in a current switching mode and wherein a third and a fourth transistor are provided whereby the current switching operation of the first and second transistor causes current switching operation of the third and fourth transistors and push pull switching of power to a load.

Abstract: An all-NPN bipolar transistor driver circuit characterized by low standby power dissipation and fast response, particularly at high input driving conditions. The bases of a pair of NPN transistors are commonly connected to an input terminal. The emitter of a third NPN transistor is connected to the collector of one transistor of the transistor pair and to an output terminal. The collector of the other transistor of the transistor pair is connected to the base of the third NPN transistor. The base and collector of the third NPN transistor are coupled to a first biasing means. The emitters of the transistor pair are connected to a second biasing means through respective resistors so that those emitters may be independently biased. The values of the biasing means are set, relative to the lowest input voltage excursion occurring at the input terminal so that no current flows through transistor pair during the lowest input voltage excursion.

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layer containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.