Abstract: A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown times.

Abstract: A current controlled oscillator circuit comprising a "variable-ratio current mirror", for providing a variable output current that varies in response to process. The "variable-ratio current mirror" having a reference MOS transistor and a mirrored MOS transistor, and the reference MOS transistor has a greater predetermined channel length than the channel length of the mirrored MOS transistor. A second current mirror is coupled to the "variable-ratio current mirror" to provide a control current that decreases in response to an increase in the variable output current of the "variable-ratio current mirror." A multi-stage ring oscillator having a plurality of series-connected inverter stages is responsive to the control current of said second current mirror for controlling the frequency of oscillation of said multi-stage ring oscillator.

Abstract: A differential delay stage for a ring oscillator utilizes a resonant circuit formed by an inductor and a capacitor consisting of two varactor diodes connected back-to-back. A common cathode connection is connected to a variable voltage source to vary the capacitance of the diodes. Other forms of capacitors may replace the varactor diodes. Varying the capacitance value varies the resulting oscillation frequency of the ring oscillator. When several delay stages, each incorporating the resonant circuit, are connected together in a ring, the net effect is to allow only a signal at the resonant frequency of the resonant circuits to propagate around the ring. Other oscillator circuits employing a resonant circuit are disclosed.

Abstract: Circuit and method of glitchless switching between asynchronous data inputs to a digital multiplexer (MUX) by maintaining and conditioning the width of the clock pulse corresponding to a first data input signal so that an output pulse is produced having a pulse width that is never narrower than the narrowest of input signals, i.e., does not produce a narrow-pulse glitch. The circuit comprises select inputs in parallel to both a MUX via a select latch device and to an edge detector having an output pulse triggering a synchronization assembly. The synchronization assembly freezes the output in the last state received from the multiplexer. The select input edge detector freezes the original D0 input at a high state until the new input D1 is cleared through the synchronization assembly.

Abstract: The present invention provides a CMOS output buffer with ECL output characteristics that allows the outputs to be terminated in any manner desired and which is not limited by the op amp settling time. The buffer establishes a bus internally for the VOH and VOL levels and then switches between the buses using transmission gates. In the disclosed embodiment of the invention, the op amp's feedback path includes a P-channel device which is either identical to or, to conserve power, a carefully scaled down equivalent of the P-channel output device.

Abstract: The present invention provides a high frequency CMOS voltage controlled oscillator circuit with gain constant and duty cycle compensation. The voltage controlled oscillator circuit includes a multi-stage ring oscillator that includes a plurality of series-connected inverter stages comprising N-channel and P-channel transistors. The ring oscillator responds to a control current signal for controlling the frequency of oscillation of the ring oscillator. A voltage-to-current converter converts a tuning voltage input signal to a corresponding output current signal that is independent of the channel strength of the N-channel and P-channel transistors. Process compensation circuitry responds to the tuning voltage input signal to provide a current dump output signal corresponding to the channel strength of the P-channel and N-channel transistors. Trip-point compensation circuit provides a net ring current signal as the current control signal to the ring oscillator.

Abstract: An emitter-coupled logic (ECL) gate configuration is provided that allows variations in the bias current for controlling propagation delay. The emitter coupled logic circuitry includes a plurality of input transistors having commonly-coupled emitters. The collector of each input transistor is connected to receive a control voltage. A current source is connected between the commonly-coupled emitters and ground. Circuitry, preferably a variable resistance, is connected between the collectors of the input transistors and a supply voltage. A bias voltage controls the charging current provided to the collectors of the ECL input transistors.