Abstract: A codeword synthesizing system and a correlation system for use with a spread spectrum communications system. In one embodiment, the codeword synthesizing system typically associated with a transmitter includes a base sequence generating subsystem, a modifier sequence generating subsystem and a concatenating subsystem. The base sequence generating subsystem is configured to create base sequences having a length less than a synthesized codeword. The modifier sequence generating subsystem is configured to create a modifier sequence, and the concatenating subsystem is configured to produce the synthesized codeword by multiplying each of the base sequences by an element of the modifier sequence. In one embodiment, the correlation system typically associated with a receiver includes a partial correlating subsystem, a memory subsystem and a combining subsystem. The partial correlating subsystem correlates base sequences of a synthesized codeword to a template and derives multiple partially correlated resultants.

Abstract: A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

Abstract: A codeword synthesizing system and a correlation system for use with a spread spectrum communications system. In one embodiment, the codeword synthesizing system typically associated with a transmitter includes a base sequence generating subsystem, a modifier sequence generating subsystem and a concatenating subsystem. The base sequence generating subsystem is configured to create base sequences having a length less than a synthesized codeword. The modifier sequence generating subsystem is configured to create a modifier sequence, and the concatenating subsystem is configured to produce the synthesized codeword by multiplying each of the base sequences by an element of the modifier sequence. In one embodiment, the correlation system typically associated with a receiver includes a partial correlating subsystem, a memory subsystem and a combining subsystem. The partial correlating subsystem correlates base sequences of a synthesized codeword to a template and derives multiple partially correlated resultants.

Abstract: A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

Abstract: The number of circuit path crossover points on boards mounting plural connected multichip modules is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a way that their inter-connecting north-east-south-west ports are successively reordered to N-S-E-W. Additionally, further advantage in reducing crossover vias may be gained by combining the reordering with a phased rotation of the modules from their nominal congruent board position. For the 4-sided module, these expedients virtually eliminate crossover vias between the east and west ports. It also provides for all MCMs a ready common bus structure located at a common interior area of the mounting board, to which the E- and W-ports are oriented. The invention is applicable to a class of multi-sided, multi-chip modules on boards with a like number of sides.

Abstract: A system is described for arraying multi-device processing nodes in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes are mounted on boards. Selective connection of ports of each board to ports of another adjacent board is effected by a routing and spacer element having internal routing paths.

Abstract: An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4.times.4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors.

Abstract: A binary tree multiprocessing array of plural signal processing elements, and having input/output for the array entirely through a root one of the processing elements, includes in each processing element thereof a hardware, pipelined, floating point, multiply/accumulate processing function for cooperating with a procesing element memory and a processing element input/output processing function to perform signal pattern matching of input digital signal sequences provided to and/or through the root processing element with respect to at least one digital signal sequence pattern stored in the memory.

Abstract: A binary full adder, including provision for carry digits, is implemented using metal-oxide semiconductor field-effect transistors (MOSFET) in the exclusive-OR configuration. The improved structure realizes economies in space occupancy, and device topology, reduction in power requirement and no loss in propagation time over prior full adders employing conventional logic structures.

Abstract: Apparatus for designating contiguous memory locations in a data memory as a circular data buffer. A limit register defines the topmost buffer location and a modulus register defines the length of the buffer. Circuitry detects violations of the upper boundary of the buffer and subtracts the buffer length from the address. Boundary violation circuitry also controls conditional execution of a data processor instruction which conditionally subtracts the buffer length from the address.