Abstract: A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple versions.

Abstract: An apparatus for two-dimensional magnetic recording includes an array reader comprising a number of read sensors configured to read data from at least one track on a storage medium, a number of two-dimensional equalizer circuits each comprising inputs for receiving signals derived from each of the read sensors, each comprising an equalized output, and a number of iterative inter-track interference cancellation circuits, each operable to cancel inter-track interference in a different one of the equalized outputs from the two-dimensional equalizer circuits.

Abstract: An apparatus for two-dimensional magnetic recording includes an array reader comprising a number of read sensors configured to read data from at least one track on a storage medium, a number of two-dimensional equalizer circuits each comprising inputs for receiving signals derived from each of the read sensors, each comprising an equalized output, and a number of iterative inter-track interference cancellation circuits, each operable to cancel inter-track interference in a different one of the equalized outputs from the two-dimensional equalizer circuits.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.

Abstract: An apparatus for storing data includes a storage medium with user data regions and with servo data regions containing preamble patterns. Servo data in the servo data regions is written with a varying clock frequency across the storage medium. The apparatus also includes a head assembly disposed in relation to the storage medium and operable to read and write data on the storage medium. The apparatus also includes a preamble detection circuit adapted to search an input stream derived from the head assembly for the preamble patterns in a number of frequency bins.

Abstract: Systems and methods relating generally to data storage, and more particularly to systems and methods for accessing and storing information using multiple sensors.

Abstract: Systems and methods are disclosed for data processing, and more particularly for equalizing a data signal during both real time (i.e., on the fly) and retry operation. The system may include a first equalizer circuit operable to equalize a first sample set, and a second equalizer circuit operable to equalize a second sample set. The system may include a third equalizer circuit operable to equalize a summed data set to yield a third equalized output. The system may include a summation circuit connected to the first equalizer circuit, the second equalizer circuit, and a switch circuit. The summation circuit is operable to sum at least the first equalized data set and the second equalized data set to yield the summed data set. The switch circuit selectively provides the third equalized data set to the summation circuit.

Abstract: Systems and method are disclosed relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. One example of the system includes a first equalizer circuit, a second equalizer circuit, a summation circuit, a first multiplication circuit, a second multiplication circuit, and a scalar calculation circuit that is capable of calculating a scalar based upon coefficients that are also provided as inputs to the first equalizer and second equalizer.

Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

Abstract: The present inventions are related to systems and methods for determining contact between two elements, and more particularly to systems and methods for determining contact between a head assembly and a storage medium.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.