Patents by Inventor Richard Rea

Richard Rea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240106881
    Abstract: Methods, systems, and devices for wireless communications are described. In a wireless audio system, a first wireless device may generate a first media stream associated with a first media mode and a second media stream associated with a second media mode, buffer the first media stream in accordance with a first latency time value for adjusting a first latency time of the first media stream and buffering the second audio stream, independently from the first media stream, in accordance with a second latency time value for adjusting a second latency time of the second media stream, and transmit a mixed media stream including the buffered first media stream mixed with the buffered second media stream to a second wireless device.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Richard Turner, Laurent Wojcieszak, Derrick Rea, Raghavendra Bhat Noojady Krishna, Bharath Kumar Tirunagaru
  • Patent number: 10679960
    Abstract: A heat and shock resistant integrated circuit (IC) of the present invention includes a base material, a metal layer disposed on the base material, a silicon die disposed on the metal layer, additive material disposed on the base material, gas filled filler material disposed between the additive material and the silicon die, and first traces electrically connecting the silicon die to the additive material. Packing of the integrated circuit provides exceptional thermal stress relief and impact protection of circuitry within the packaging.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 9, 2020
    Assignee: Hall Labs LLC
    Inventors: David R. Hall, Marshall Soares, Derek Maxwell, Richard Rea
  • Publication number: 20180301400
    Abstract: A heat and shock resistant integrated circuit (IC) of the present invention includes a base material, a metal layer disposed on the base material, a silicon die disposed on the metal layer, additive material disposed on the base material, gas filled filler material disposed between the additive material and the silicon die, and first traces electrically connecting the silicon die to the additive material. Packing of the integrated circuit provides exceptional thermal stress relief and impact protection of circuitry within the packaging.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Inventors: David R. Hall, Marshall Soares, Derek Maxwell, Richard Rea