Patents by Inventor Richard RICHMOND
Richard RICHMOND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180349147Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: ApplicationFiled: February 20, 2018Publication date: December 6, 2018Inventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
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Publication number: 20180260333Abstract: Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.Type: ApplicationFiled: February 23, 2018Publication date: September 13, 2018Inventor: Richard Richmond
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Publication number: 20180246725Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: ApplicationFiled: February 20, 2018Publication date: August 30, 2018Inventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
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Patent number: 9996912Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: GrantFiled: October 31, 2016Date of Patent: June 12, 2018Assignee: Linear Algebra Technologies LimitedInventors: Richard Richmond, Cormac Brick, Brendan Barry, David Moloney
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Patent number: 9934043Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: GrantFiled: November 18, 2013Date of Patent: April 3, 2018Assignee: Linear Algebra Technologies LimitedInventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry
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Patent number: 9916252Abstract: Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.Type: GrantFiled: May 19, 2015Date of Patent: March 13, 2018Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventor: Richard Richmond
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Patent number: 9910675Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: GrantFiled: August 12, 2014Date of Patent: March 6, 2018Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
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Patent number: 9727113Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: GrantFiled: August 12, 2014Date of Patent: August 8, 2017Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: Brendan Barry, Richard Richmond, Fergal Connor, David Moloney
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Publication number: 20170116718Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: ApplicationFiled: October 31, 2016Publication date: April 27, 2017Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
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Publication number: 20160342521Abstract: Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.Type: ApplicationFiled: May 19, 2015Publication date: November 24, 2016Applicant: Linear Algebra Technologies LimitedInventor: Richard RICHMOND
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Patent number: 9483706Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: GrantFiled: January 8, 2015Date of Patent: November 1, 2016Assignee: Linear Algebra Technologies LimitedInventors: Richard Richmond, Cormac Brick, Brendan Barry, David Moloney
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Publication number: 20160203384Abstract: One of the challenges in bringing computational imaging to a mass market is that computational imaging is inherently computationally expensive. The computational challenges associated with computational imaging are apparent with the computation of a histogram of gradient descriptors. Oftentimes, generating a histogram of gradient descriptors involves computing gradients of an image, binning the gradients according to their orientation, and, optionally, normalizing the bins using a non-linear function. Because each of these operations is expensive, the histogram of gradient descriptor computations is generally computationally expensive and is difficult to implement in a power efficient manner for mobile applications. The present application discloses a computing device that can provide a low-power, highly capable computing platform for computing a histogram of gradient descriptors.Type: ApplicationFiled: January 8, 2015Publication date: July 14, 2016Inventors: Richard RICHMOND, Cormac BRICK, Brendan BARRY, David MOLONEY
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Patent number: 9196017Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.Type: GrantFiled: November 15, 2013Date of Patent: November 24, 2015Assignee: Linear Algebra Technologies LimitedInventors: David Donohoe, Brendan Barry, David Moloney, Richard Richmond, Fergal Connor
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Patent number: 9146747Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: GrantFiled: November 18, 2013Date of Patent: September 29, 2015Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David Moloney, Richard Richmond, David Donohoe, Brendan Barry, Cormac Brick, Ovidiu Andrei Vesa
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Publication number: 20150138405Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David DONOHOE, Brendan BARRY, David MOLONEY, Richard RICHMOND, Fergal CONNOR
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Publication number: 20150046677Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: ApplicationFiled: November 18, 2013Publication date: February 12, 2015Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY
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Publication number: 20150046678Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.Type: ApplicationFiled: November 18, 2013Publication date: February 12, 2015Applicant: Linear Algebra Technologies LimitedInventors: David MOLONEY, Richard RICHMOND, David DONOHOE, Brendan BARRY, Cormac BRICK, Ovidiu Andrei VESA
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Publication number: 20150046674Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: ApplicationFiled: August 12, 2014Publication date: February 12, 2015Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY
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Publication number: 20150046675Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.Type: ApplicationFiled: August 12, 2014Publication date: February 12, 2015Inventors: Brendan BARRY, Richard RICHMOND, Fergal CONNOR, David MOLONEY