Abstract: Described is a method and system for creating model components, such as business model components, using gestures that are input to a computer system. In an exemplary embodiment, the gestures are input to a computer system with a mouse device, but in general the gestures can be input via any suitable information input device. The gestures have at least three attributes. First, the gesture is orientation sensitive. This requires that the meaning of the gesture depends on the direction in which the gesture is made. Second, the gesture is context sensitive. This requires that the meaning of the gesture depends on the starting point and the ending point of the gesture. Third, the gesture is coincident input sensitive. This requires that the meaning of the gesture depends on the state of additional input from the user.

Abstract: An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit.

Abstract: An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit.

Abstract: Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the computation engine. The computation engine is controlled by an MCC memory-centric controller that provides microcoded operation of the engine independently of the CPU. Essential interfacing between the processor bus and the computation engine includes storing microcode in a separate memory accessible to the MCC controller, or downloading microcode from the CPU/processor bus as needed for a specific task. The MCC controller can reconfigure the computation engine, such as memory block allocation, word size, etc. under microcode control, so that new or user-proprietary algorithms such as those used in dsp can be implemented using a standard computation engine without redesign. Execution of selected tasks on the computation engine is triggered automatically by decoding instructions that appear on the processor bus.

Abstract: Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.