Patents by Inventor Richard Ruddell
Richard Ruddell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9582278Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: October 9, 2008Date of Patent: February 28, 2017Assignee: Cadence Design Systems, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
-
Patent number: 8161432Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: October 9, 2008Date of Patent: April 17, 2012Assignee: Tensilica, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
-
Publication number: 20090177876Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: ApplicationFiled: October 9, 2008Publication date: July 9, 2009Inventors: Albert Ren-Rui WANG, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
-
Publication number: 20090172630Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: ApplicationFiled: October 9, 2008Publication date: July 2, 2009Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
-
Publication number: 20090125866Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.Type: ApplicationFiled: November 13, 2008Publication date: May 14, 2009Inventors: ALBERT REN-RUI WANG, RICHARD RUDDELL, DAVID WILLIAM GOODWIN, EARL A. KILLIAM, NUPUR BHATTACHARYYA, MARINES PUIG MEDINA, WALTER DAVID LICHTENSTEIN, PAVLOS KONAS, RANGARAJAN SRINIVASAN, CHRISTOPHER MARK SONGER, AKILESH PARAMESWAR, DROR E. MAYDAN, RICARDO E. GONZALEZ
-
Patent number: 7437700Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: November 16, 2005Date of Patent: October 14, 2008Assignee: Tensilica, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
-
Publication number: 20080220056Abstract: The present invention is based on the finding that the artificial induction of hepatic stellate cell (HSC) apoptosis in vivo can promote the resolution of liver fibrosis. Thus, the present invention provides methods for treating liver disease in a subject involving administration of an inducer of apoptosis which is capable of selectively inducing hepatic stellate cell apoptosis in the liver of the subject or of an agent which is capable of giving rise to such an inducer in the subject. In addition, the invention provides methods for treating liver fibrosis in a subject comprising the selective delivery of an inducer of apoptosis specifically to the hepatic stellate cells of the subject or of an agent which is capable of giving rise to an inducer of hepatic stellate cell apoptosis.Type: ApplicationFiled: May 21, 2007Publication date: September 11, 2008Applicant: UNIVERSITY OF SOUTHAMPTONInventors: Michael James Paul Arthur, Derek Austin Mann, John Peter Iredale, Christopher Benyon, Frank Murphy, Fiona Oakley, Richard Ruddell, Matthew Christopher Wright
-
Automated processor generation system for designing a configurable processor and method for the same
Publication number: 20060101369Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: ApplicationFiled: November 16, 2005Publication date: May 11, 2006Inventors: Albert Wang, Richard Ruddell, David Goodwin, Earl Killian, Nupur Bhattacharyya, Marines Medina, Walter Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Songer, Akilesh Parameswar, Dror Maydan, Ricardo Gonzalez -
Automated processor generation system for designing a configurable processor and method for the same
Patent number: 7036106Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.Type: GrantFiled: February 17, 2000Date of Patent: April 25, 2006Assignee: Tensilica, Inc.Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez -
Publication number: 20050191302Abstract: The present invention is based on the finding that the artificial induction of hepatic stellate cell (HSC) apoptosis in vivo can promote the resolution of liver fibrosis. Thus, the present invention provides methods for treating liver disease in a subject involving administration of an inducer of apoptosis which is capable of selectively inducing hepatic stellate cell apoptosis in the liver of the subject or of an agent which is capable of giving rise to such an inducer in the subject. In addition, the invention provides methods for treating liver fibrosis in a subject comprising the selective delivery of an inducer of apoptosis specifically to the hepatic stellate cells of the subject or of an agent which is capable of giving rise to an inducer of hepatic stellate cell apoptosis.Type: ApplicationFiled: August 28, 2003Publication date: September 1, 2005Applicant: UNIVERSITY OF SOUTHAMPTONInventors: Michael Arthur, Derek Mann, John Iredale, Christopher Benyon, Frank Murphy, Fiona Oakley, Richard Ruddell, Matthew Wright
-
Patent number: 6477697Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. The standardized language is capable of handling instruction set extensions which modify processor state or use configurable processors. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: May 28, 1999Date of Patent: November 5, 2002Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Richard Ruddell, Albert Ren-Rui Wang