Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: Circuits for measuring a leakage current of one or more capacitors coupled to a power supply line that powers an apparatus, such as a storage device, are disclosed. In one embodiment, the circuit includes first and second resistors between the power supply line, and first and second respective switches to ground. A controller may charge the voltage line to a first voltage. Thereafter, the controller discharges the first voltage to a second voltage via the first resistor during a first identified time. After recharging the voltage line, the controller then discharge the first voltage to the second voltage via at least the second resistor during a second identified time. The controller determines the parasitic resistance using the first and second identified times, and then the leakage current from the parasitic resistance.

Abstract: Circuits for measuring a leakage current of one or more capacitors coupled to a power supply line that powers an apparatus, such as a storage device, are disclosed. In one embodiment, the circuit includes first and second resistors between the power supply line, and first and second respective switches to ground. A controller may charge the voltage line to a first voltage. Thereafter, the controller discharges the first voltage to a second voltage via the first resistor during a first identified time. After recharging the voltage line, the controller then discharge the first voltage to the second voltage via at least the second resistor during a second identified time. The controller determines the parasitic resistance using the first and second identified times, and then the leakage current from the parasitic resistance.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Abstract: A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Abstract: The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Abstract: Disclosed is a method, system, and program for generating a table for enhancing the print quality of input raster pel data. An output value is generated for different patterns of pel data. Each output value indicates a sub-pulse width power to charge a sub-pel region within a pel and position information indicating the justification of the sub-pel region within the pel. A look-up table is formed from the generated output values that enhances print quality.

Abstract: A method triggers a printer (106) to receive a signal (300) from a print engine (202) indicating the initiation of the transmission of print data; transmits a shorter signal (302) to a printer ASIC (204), in response to receiving a first signal; receives a first line of data to be printed from the printer ASIC (204); receives a second signal from the print engine (202); transmits a second shorter signal to the printer ASIC (204), in response to receiving a signal; receives a second line of data to be printed from the printer ASIC (204); and transmits the first line of data to the print engine (202). This allows a slower printer ASIC (204) to be used with a faster print engine (202).

Abstract: Disclosed is a method, system, and program for modifying raster pel data according to different types of filtering operations. At least two tables are maintained in memory. At least two of the tables provide output pel values for at least two different types of filtering operations based on input pet values. A plurality of pets are read from raster data for a print job. A determination is made of an entry in one table based on the plurality of read pels to determine at least one output pet value that accomplishes the filtering operation associated with the table. At least two of the tables may be used in the same page of raster data to perform the different filtering operations associated with the at least two tables used within one page. The at least one output pel value is used to generate a pulse to control a printer apparatus.

Abstract: Disclosed is a method, system, and program for reducing toner in an image comprised of raster pel data. A determination is made of pels surrounding subject pels. For each subject pel, a sub-pulse width power is generated to charge a sub-pel region within the subject pel based on a pattern of the surrounding pels of the subject pel. Further, for each subject pel, position information is generated indicating an alignment of the sub-pel region in the pel. The position information is used to position the sub-pel region produced by the sub-pulse width power in the pel.

Abstract: A method and apparatus for identifying a version of an electronic assembly using a unique embedded identification signature for each different version is disclosed. A unique instruction code is loaded on each type or version of a electronic assembly. The unique embedded identification signature allows common instruction code over a family (different types) and versions (revisions) of an electronic assembly. Allowing common code is must less costly to maintain and takes very little board space.

Abstract: A method triggers a printer (106) to receive a signal (300) from a print engine (202) indicating the initiation of the transmission of print data; transmits a shorter signal (302) to a printer ASIC (204), in response to receiving a first signal; receives a first line of data to be printed from the printer ASIC (204); receives a second signal from the print engine (202); transmits a second shorter signal to the printer ASIC (204), in response to receiving a signal; receives a second line of data to be printed from the printer ASIC (204); and transmits the first line of data to the print engine (202). This allows a slower printer ASIC (204) to be used with a faster print engine (202).