Patents by Inventor Richard S Perry
Richard S Perry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11939347Abstract: Compounds and methods of using said compounds, singly or in combination with additional agents, and pharmaceutical compositions of said compounds for the treatment of viral infections are disclosed.Type: GrantFiled: June 23, 2021Date of Patent: March 26, 2024Assignee: Gilead Sciences, Inc.Inventors: Daniel H. Byun, Byoung-Kwon Chun, Michael O. Clarke, Petr Jansa, Rao V. Kalla, Dmitry Koltun, Richard L. Mackman, Thao D. Perry, Dustin S. Siegel, Scott P. Simonovich
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Publication number: 20230299516Abstract: A back-to-back ultra-slim module (USM) includes an inline USM (USMi) connector and a top mount USM (USMt) connector. The back-to-back USM assembly can be made as a double-sided module to allow a stacked module configuration to save system area. The stacked module has a USMi module inline with the system board on one side of the system board, and a USMt module vertically offset from the other side of the system board. The stacked module can have a thermal layer between the USMi module and the USMt module.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: Intel CorporationInventors: Amarjeet KUMAR, Navneet Kumar SINGH, I, Samarth ALVA, Richard S. PERRY, Christopher WEST
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Publication number: 20220408561Abstract: A novel method and interface are provided to generalize power delivery (PD) solutions and allow OEMs and suppliers to easily replace PD solutions using the same design and layout without having to re-spin the motherboard. This is achieved by defining a new interface and ball-out which support dual port PD solution that meet the system requirements. The embodiments employ an interposer to unify different PD solutions. The interposer is part of a unique Land Grid Array (LGA) soldered down solution with pre-defined interface employing a generic pinout to support PD solutions for dual type-C ports from different vendors. The interposer includes an LGA having a pattern of pads that is coupled to a LGA on a platform PCB with a matching pattern.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Inventors: Tomer SAVARIEGO, Richard S. PERRY, Oren HUBER, Venkataramani GOPALAKRISHNAN
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Patent number: 11374322Abstract: Techniques for fabricating end-fire antennas are described. An example of an electronic device with an end-fire antenna includes a housing of the electronic device, and a circuit board comprising electronic components of the mobile electronic device. The circuit board is parallel with the major plane of the housing. The electronic device includes an antenna coupled to the circuit board. At least a portion of the antenna is oriented perpendicular to the first circuit board to generate a radiation pattern with an amplitude that is greater in the end-fire direction compared to the broadside direction.Type: GrantFiled: September 30, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Omer Asaf, Sidharth Dalmia, Trang Thai, Josef Hagn, Richard S. Perry, Jonathan C. Jensen, Raanan Sover
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Publication number: 20220083109Abstract: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.Type: ApplicationFiled: July 26, 2021Publication date: March 17, 2022Inventors: Raanan Sover, Eytan Mann, Rafi Ben-Tal, Richard S. Perry
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Publication number: 20220077609Abstract: A connector to connect an electronic module to an edge of a first electronic circuit board is described. The module has a second electronic circuit board. The connector has a top part that houses a first row of I/Os. The top part is to be placed on a surface of the first electronic circuit board. The connector has a bottom part that houses a second row of I/Os. The bottom part is to be placed on an opposite surface of the first electronic circuit board, wherein, the top and bottom parts form inner and outer stand-offs when mater together. The inner stand-off is to reside within a through hole of the first electronic circuit board. The outer stand-off is to reside within free space off the edge of the first electronic circuit board. The second electronic circuit board is to be pressed in between the first row of I/Os and the second row of I/Os when the module is connected to the connector.Type: ApplicationFiled: September 20, 2021Publication date: March 10, 2022Inventors: Navneet Kumar SINGH, Aiswarya M. PIOUS, Richard S. PERRY, Amarjeet KUMAR, Siva Prasad JANGILI GANGA, Gaurav HADA, Sushil PADMANABHAN, Konika GANGULY
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Patent number: 11073873Abstract: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.Type: GrantFiled: March 25, 2020Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Raanan Sover, Eytan Mann, Rafi Ben-Tal, Richard S Perry
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Publication number: 20210119363Abstract: A board-to-board connector includes electrical leads to bridge from one board to another board, to interconnect pads on one surface of the boards. The boards can interconnect while one board is vertically offset from the other board with a top mount connector. The connector includes a lead frame having the electrical leads and the connector includes an alignment frame to hold the lead frame. The lead frame includes leads that have contact arms that are vertically offset from each other. The connector includes a conductive case to secure over the alignment frame. The connector includes screw holes to allow screws to secure the connector in place against the boards and ensure electrical connection between the pads on the two boards through the electrical leads of the connector. The alignment frame includes posts to mate with alignment holes in the boards.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Inventors: Richard S. PERRY, Robert SCHUM
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Publication number: 20210119361Abstract: A board-to-board connector includes electrical leads to bridge from one board to another board, to interconnect pads on one surface of the boards. The boards can interconnect while aligned in substantially the same plane with an inline connector. The connector includes a lead frame having the electrical leads and the connector includes an alignment frame to hold the lead frame. The connector includes a conductive case to secure over the alignment frame. The connector includes screw holes to allow screws to secure the connector in place against the boards and ensure electrical connection between the pads on the two boards through the electrical leads of the connector. The alignment frame includes posts to mate with alignment holes in the boards.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Inventors: Richard S. PERRY, Robert SCHUM
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Publication number: 20200203834Abstract: Techniques for fabricating end-fire antennas are described. An example of an electronic device with an end-fire antenna includes a housing of the electronic device, and a circuit board comprising electronic components of the mobile electronic device. The circuit board is parallel with the major plane of the housing. The electronic device includes an antenna coupled to the circuit board. At least a portion of the antenna is oriented perpendicular to the first circuit board to generate a radiation pattern with an amplitude that is greater in the end-fire direction compared to the broadside direction.Type: ApplicationFiled: September 30, 2017Publication date: June 25, 2020Applicant: INTEL CORPORATIONInventors: Omer Asaf, Sidharth Dalmia, Trang Thai, Josef Hagn, Richard S. Perry, Jonathan C. Jensen, Raanan Sover
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Patent number: 8706049Abstract: Disclosed are integration approaches for mm-wave planar phased array type architectures using multilayer substrate technologies. For instance, an apparatus may include a plurality of substrate layers, an integrated circuit, and a connector module. The plurality of substrate layers includes a first substrate layer having one or more phased array elements. The integrated circuit exchange one or more radio frequency (RF) signals (e.g., mm-wave signals) with the one or more phased array elements. The connector module exchange further signals with the integrated circuit that correspond to the one or more RF signals. For example, these further signals may be baseband or intermediate frequency (IF) signals.Type: GrantFiled: December 31, 2008Date of Patent: April 22, 2014Assignee: Intel CorporationInventors: Debabani Choudhury, Richard S. Perry
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Publication number: 20100164783Abstract: Disclosed are integration approaches for mm-wave planar phased array type architectures using multilayer substrate technologies. For instance, an apparatus may include a plurality of substrate layers, an integrated circuit, and a connector module. The plurality of substrate layers includes a first substrate layer having one or more phased array elements. The integrated circuit exchange one or more radio frequency (RF) signals (e.g., mm-wave signals) with the one or more phased array elements. The connector module exchange further signals with the integrated circuit that correspond to the one or more RF signals. For example, these further signals may be baseband or intermediate frequency (IF) signals.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Debabani Choudhury, Richard S. Perry
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Patent number: 7724542Abstract: Certain embodiments relate to electronic devices and methods for forming electronic devices having a component shielded by a reworkable RF shield. The RF shield may be positioned to surround one or more components on a substrate. The RF shield may include a plurality of sidewalls and a top wall, the plurality of sidewalls including bumps extending outward therefrom. A portion of the top wall may be removed from the RF shield. The one or more components positioned under the top wall of the RF shield may be repaired or replaced if necessary. A lid may then be positioned over the removed portion of the top wall and placed so that the bumps engage apertures in the lid and result in the lid being rigidly coupled to the sidewalls. In one aspect of certain embodiments, a groove may be formed on one or more surfaces of the top wall. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2006Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Ron W. Gallahan, Richard S. Perry, Michael Stewart, Pedro A. Gutierrez, Donald M. Hammon
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Patent number: 7656151Abstract: An electronic package includes a printed circuit board having a primary side, and a secondary side. A component, having a main body, is attached to the primary side of the printed circuit board. A pad is attached to the main body of the component. The printed circuit board has an opening therein positioned near the pad.Type: GrantFiled: September 18, 2007Date of Patent: February 2, 2010Assignee: Intel CorporationInventor: Richard S Perry
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Publication number: 20080158849Abstract: Certain embodiments relate to electronic devices and methods for forming electronic devices having a component shielded by a reworkable RF shield. The RF shield may be positioned to surround one or more components on a substrate. The RF shield may include a plurality of sidewalls and a top wall, the plurality of sidewalls including bumps extending outward therefrom. A portion of the top wall may be removed from the RF shield. The one or more components positioned under the top wall of the RF shield may be repaired or replaced if necessary. A lid may then be positioned over the removed portion of the top wall and placed so that the bumps engage apertures in the lid and result in the lid being rigidly coupled to the sidewalls. In one aspect of certain embodiments, a groove may be formed on one or more surfaces of the top wall. Other embodiments are described and claimed.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Ron W. Gallahan, Richard S. Perry, Michael Stewart, Pedro A. Gutierrez, Donald M. Hammon
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Patent number: 7276921Abstract: A test device includes an element having a surface for contacting a first plane, and a probe having a free end positioned in a second plane. The element of the test having the surface to contact the first plane includes features for contacting a ground plane. The length of the probe in the test device is greater than the length of the element having a surface for contacting the first plane. An electronic package includes a printed circuit board having a primary side, and a secondary side. A component, having a main body, is attached to the primary side of the printed circuit board. A pad is attached to the main body of the component. The printed circuit board has an opening therein positioned near the pad. The probe passes through the opening in the printed circuit board to contact the pad from the secondary side of the printed circuit board.Type: GrantFiled: June 30, 2003Date of Patent: October 2, 2007Assignee: Intel CorporationInventor: Richard S Perry
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Publication number: 20040263189Abstract: A test device includes an element having a surface for contacting a first plane, and a probe having a free end positioned in a second plane. The element of the test having the surface to contact the first plane includes features for contacting a ground plane. The length of the probe in the test device is greater than the length of the element having a surface for contacting the first plane. An electronic package includes a printed circuit board having a primary side, and a secondary side. A component, having a main body, is attached to the primary side of the printed circuit board. A pad is attached to the main body of the component. The printed circuit board has an opening therein positioned near the pad. The probe passes through the opening in the printed circuit board to contact the pad from the secondary side of the printed circuit board.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventor: Richard S. Perry