Patents by Inventor Richard S. WU
Richard S. WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10636457Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: February 27, 2019Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Publication number: 20190259427Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: February 27, 2019Publication date: August 22, 2019Inventors: Harold PILO, Richard S. WU
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Patent number: 10381052Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: February 20, 2018Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Publication number: 20180174645Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Harold PILO, Richard S. WU
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Patent number: 9953698Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: October 30, 2017Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Publication number: 20180068711Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: October 30, 2017Publication date: March 8, 2018Inventors: Harold PILO, Richard S. WU
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Patent number: 9881666Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: December 8, 2015Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Patent number: 9734891Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: December 8, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Patent number: 9734892Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: December 8, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold Pilo, Richard S. Wu
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Patent number: 9679635Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: December 8, 2015Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Harold Pilo, Richard S. Wu
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Patent number: 9318162Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: GrantFiled: August 4, 2014Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Harold Pilo, Richard S. Wu
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Patent number: 9311978Abstract: A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and arranged to: apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to the gate of the header device to deactivate the bank. The circuit also includes a precharge circuit that charges the gate of the header device to a precharge voltage that is greater than ground and less than the regulated voltage.Type: GrantFiled: October 23, 2013Date of Patent: April 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Harold Pilo, Richard S. Wu
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Publication number: 20160093359Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Harold PILO, Richard S. WU
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Publication number: 20160093361Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Harold PILO, Richard S. WU
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Publication number: 20160093360Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Harold PILO, Richard S. WU
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Publication number: 20160086658Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: December 8, 2015Publication date: March 24, 2016Inventors: Harold PILO, Richard S. WU
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Publication number: 20160035397Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.Type: ApplicationFiled: August 4, 2014Publication date: February 4, 2016Inventors: Harold PILO, Richard S. WU
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Publication number: 20150168982Abstract: A voltage regulation circuit and method where a pre-charge device (PCD) and a power gate device (PGD) are connected to a voltage line that supplies power to at least one additional device. The PCD pre-charges the line toward a supply voltage (Vdd) and PGD limits voltage changes on the voltage line caused by leakage current in the additional device(s) and does so differently under different leakage conditions. Specifically, the PGD is controlled by a variable reference voltage (Vref), which is closer to Vdd when a leakage condition is low relative to when the leakage condition is high. Since Vref is relatively high when the leakage condition is low and relatively low when the leakage condition is high, the power gate device will turn on after a smaller amount of voltage change on the voltage line when the leakage condition is low as compared to when the leakage condition is high.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Harold Pilo, Richard S. Wu
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Patent number: 9058046Abstract: A voltage regulation circuit and method where a pre-charge device (PCD) and a power gate device (PGD) are connected to a voltage line that supplies power to at least one additional device. The PCD pre-charges the line toward a supply voltage (Vdd) and PGD limits voltage changes on the voltage line caused by leakage current in the additional device(s) and does so differently under different leakage conditions. Specifically, the PGD is controlled by a variable reference voltage (Vref), which is closer to Vdd when a leakage condition is low relative to when the leakage condition is high. Since Vref is relatively high when the leakage condition is low and relatively low when the leakage condition is high, the power gate device will turn on after a smaller amount of voltage change on the voltage line when the leakage condition is low as compared to when the leakage condition is high.Type: GrantFiled: December 16, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Harold Pilo, Richard S. Wu
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Publication number: 20150109873Abstract: A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and arranged to: apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to the gate of the header device to deactivate the bank.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold PILO, Richard S. WU