Patents by Inventor Richard S. Zarr

Richard S. Zarr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5597469
    Abstract: Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: January 28, 1997
    Assignee: International Business Machines Corporation
    Inventors: Charles F. Carey, Kenneth M. Fallon, Voya R. Markovich, Douglas O. Powell, Gary P. Vlasak, Richard S. Zarr
  • Patent number: 5418689
    Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventors: Warren A. Alpaugh, Voya R. Markovich, Ajit K. Trivedi, Richard S. Zarr
  • Patent number: 5316788
    Abstract: Process is described for applying large quantities of solder to small areas, such as the lands in a high density card, to which it is intended to surface mount electronic devices or directly attach circuitized chips. The land area is temporarily extended by depositing a relatively thin layer of metal beyond the perimeter of the land, wave soldering to deposit excess solder on the extended land region, and reflow, whereby the thin layer of metal dissolves into the solder, causing the solder to retract to the dimensions of the original land. Because the volume of solder is increased, the strength and reliability of the solder joint is greatly improved.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: Eric P. Dibble, Steven L. Hanakovic, Voya R. Markovich, Daniel S. Niedrich, Gary P. Vlasak, Richard S. Zarr, Richard C. Senger
  • Patent number: 4820643
    Abstract: The effectiveness of a palladium-tin catalyst for subsequent plating thereon is determined by employing cyclic voltammetry.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: April 11, 1989
    Assignee: International Business Machines Corporation
    Inventors: William J. Amelio, Kenneth R. Czarnecki, Gary K. Lemon, Voya Markovich, Carlos J. Sambucetti, Richard S. Zarr