Abstract: An arrangement for frequency division of a symmetrical pulse train by N/2 where N is an odd integer greater than 1; this arrangement does not require the use of any one-shot multivibrators or delay elements and employs only log.sub.2 (N+1) flip-flops in its design. In one embodiment a two state gating circuit selectively allows either the input pulse train or its inverse to be fed to a modulo (N+1)/2 counter. The state of the gating circuit is controlled by a flip-flop which toggles whenever the counter reaches its maximum count. In addition, the counter produces an output pulse as it advances through each of its counting sequences. Thus, the counter, which advances in response to falling pulse edges, alternates between counting falling edges of the input pulse train and the inverted input pulse train thereby counting to N+1 in N pulse periods while yielding two equally-spaced output pulses.