Patents by Inventor Richard Schenker
Richard Schenker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113177Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Sukru Yemenicioglu, Quan Shi, Marni Nabors, Charles H. Wallace, Xinning Wang, Tahir Ghani, Andy Chih-Hung Wei, Mohit K. Haran, Leonard P. Guler, Sivakumar Venkataraman, Reken Patel, Richard Schenker
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Patent number: 11948874Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.Type: GrantFiled: June 26, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
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Publication number: 20240071913Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Intel CorporationInventors: June Choi, Richard Schenker, Charles H. Wallace, Nikhil J. Mehta, Clifford L. Ong
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INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
Publication number: 20240038661Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Applicant: Intel CorporationInventors: Manish CHANDHOK, Richard SCHENKER, Tristan TRONIC -
Interconnects having a portion without a liner material and related structures, devices, and methods
Patent number: 11837542Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: GrantFiled: January 24, 2022Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Manish Chandhok, Richard Schenker, Tristan Tronic -
Publication number: 20230369399Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Ehren MANNEBACH, Anh PHAN, Aaron LILAK, Willy RACHMADY, Gilbert DEWEY, Cheng-Ying HUANG, Richard SCHENKER, Hui Jae YOO, Patrick MORROW
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Patent number: 11764263Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.Type: GrantFiled: January 4, 2019Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Ehren Mannebach, Anh Phan, Aaron Lilak, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang, Richard Schenker, Hui Jae Yoo, Patrick Morrow
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Patent number: 11569231Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.Type: GrantFiled: March 15, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Stephen D Snyder, Leonard Guler, Richard Schenker, Michael K Harper, Sam Sivakumar, Urusa Alaan, Stephanie A Bojarski, Achala Bhuwalka
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Patent number: 11462469Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.Type: GrantFiled: September 27, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Kevin L. Lin, Nafees A. Kabir, Richard Schenker
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Patent number: 11424160Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.Type: GrantFiled: February 13, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick Morrow, Jeffery Bielefeld, Gilbert Dewey, Hui Jae Yoo, Nafees Kabir
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INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
Publication number: 20220148967Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: INTEL CORPORATIONInventors: Manish CHANDHOK, Richard SCHENKER, Tristan TRONIC -
Patent number: 11300885Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.Type: GrantFiled: July 25, 2018Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Robert Bristol, Guojing Zhang, Tristan Tronic, John Magana, Chang Ju Choi, Arvind Sundaramurthy, Richard Schenker
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Interconnects having a portion without a liner material and related structures, devices, and methods
Patent number: 11264325Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: GrantFiled: September 28, 2017Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Manish Chandhok, Richard Schenker, Tristan Tronic -
Publication number: 20210407895Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
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Publication number: 20200295002Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: Stephen D. Snyder, Leonard Guler, Richard Schenker, Michael K. Harper, Sam Sivakumar, Urusa Alaan, Stephanie A. Bojarski, Achala Bhuwalka
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Publication number: 20200258778Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Applicant: INTEL CORPORATIONInventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick Morrow, Jeffery Bielefeld, Gilbert Dewey, Hui Jae Yoo, Nafees Kabir
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Publication number: 20200219970Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Ehren Mannebach, Anh Phan, Aaron Lilak, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang, Richard Schenker, Hui Jae Yoo, Patrick Morrow
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INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
Publication number: 20200126912Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: ApplicationFiled: September 28, 2017Publication date: April 23, 2020Applicant: INTEL CORPORATIONInventors: Manish Chandhok, Richard Schenker, Tristan Tronic -
Publication number: 20200105662Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Applicant: INTEL CORPORATIONInventors: Kevin L. Lin, Nafees A. Kabir, Richard Schenker
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Publication number: 20200033736Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Robert BRISTOL, Guojing ZHANG, Tristan TRONIC, John MAGANA, Chang Ju CHOI, Arvind SUNDARAMURTHY, Richard SCHENKER