Abstract: Systems and methods to account for latency associated with remote driving applications may include a vehicle having an imaging device and a teleoperator station in communication with each other via a network. Imaging data that is captured by the imaging device may be transmitted to the teleoperator station for presentation to a teleoperator. In order to account for latency in the transmission, receipt, processing, and presentation of the imaging data, one or more visualizations of the vehicle, with various visual characteristics, may be rendered within or overlaid onto the imaging data, in order to facilitate safe and reliable remote operation of the vehicle by the teleoperator at the teleoperator station.

Abstract: Apparatus and methods for transceivers are provided herein. In a first aspect, an observation receiver is implemented to detect common-mode local oscillator (LO) leakage while the observation receiver performs other functions. In a second aspect, a transceiver is implemented with an LO leakage compensation circuit that compensates a transmitter for LO leakage using a digital filter, such as a Kalman filter, that combines differential LO leakage observations with common-mode LO leakage observations. In a third aspect, a transmitter includes multiple local loopback paths including a first loopback path after a variable gain amplifier (VGA) and a second loopback path before the VGA.

Abstract: A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

Abstract: A processor system having a cache memory. The replacement policy for the cache is augmented with a consideration of priority so that higher priority items are not displaced by lower priority items. The priority based replacement policy can be used to allow processes that are of lower priority to share the same cache with processes that are of higher priority. A processor including digital signal processing and general purpose logic function is shown to employ the priority based replacement policy to allow processes executing generalized logic functions to use the cache when not needed for digital signal processing operations that are time critical. A processor having digital signal processing capability is shown to employ the priority system to reserve a block of memory configured for a cache. The block of memory is reserved by setting the priority of those cache locations to a priority higher than any other executing process.

Abstract: Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

Abstract: A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a particular external address. Access to the data array is necessary to determine the actual value. Access of the data array overlaps access to the tag array. Access to the data array includes a step in which the charge stored on column lines corresponding to multiple ways within the data array is altered based on information stored in the memory. This step occurs while the tag array is being operated. Access to the data array includes a second step of sensing one of the state of charge on a selected column line. Sensing occurs after the value has been read from the tag array and the value in the tag array is used to indicate which, if any way in the data array to sense.

Abstract: An electronic memory device includes at least one memory cell, a write circuit that defines an output node and mediates a discharge associated with a write operation flowing to the output node, and a write strength selection circuit that modifies at least one characteristic of the discharge. A method for testing data retention of an electronic memory device includes providing a write circuit, storing a value in at least one memory cell of the memory device, directing a weak write operation to the at least one memory cell, and sensing the memory cell to determine if the stored value changed in response to the weak write operation.

Abstract: A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

Abstract: When measuring speed over ground by means of microwave Doppler radar, signal noise, switching spikes and nearby reflectors reduce the measurement accuracy. In order to avoid these disadvantages, a reference signal which recurs with the period T.sub.0 and a target signal which follows the reference signal after a time interval T.sub.s are emitted via an antenna. That part of the reference signal which has already been received again during transmission of the target signal is subtracted from the target signal which is received later. The difference signal obtained in this way is a measurement signal from which interference spikes, signal noise and nearby reflectors have been largely removed.