Abstract: PDE4 inhibition is achieved by novel compounds, e.g., N-substituted aniline and diphenylamine analogs.

Abstract: Described herein are compounds having the general formula: ##STR1## wherein: Ar.sup.1 and Ar.sup.2 are independently selected aryl groups, optionally substituted with substituents selected from the group consisting of alkyl, cycloalkyl, alkoxy, alkanoyl, aralkyl, aralkyloxy, halo, NO.sub.2, Ph, CF.sub.3, CN, OH, methylenedioxy, ethylenedioxy, SO.sub.2 NRR', NRR', CO.sub.2 R (where R and R' are independently selected from the group consisting of H and alkyl) and a second aryl group, which may be substituted as above;wherein any cycloalkyl or aryl substituent is linked to Ar.sup.1 or Ar.sup.2 by a bridging element which may be a single bond, a vinylene group, an ethynylene group, a Z group, a --Z--(CH.sub.2).sub.n -- group, a --(CH.sub.2).sub.n --Z-- group, or a --Z--(CH.sub.2).sub.n --Z-- group, where Z represents an O atom, a S atom, an NH group or an N-alkyl group, and n is an integer from 1 to 4;wherein Ar.sup.1 and Ar.sup.

Abstract: A VLSI IC's signals as they appear at the signal via pads on the back side of a mother board may be probed with the aid of a backing plate that is a piece of multi-layer printed circuit board material thick enough to be sufficiently stiff for the purpose. The multi-layer PCB backing plate has front side pads and vias in at least those locations in the LGA (of signal via pads) corresponding physically to signals that are of interest for probing, and if such a subset is unknown ahead of time, the entire LGA of signal vias pads may be represented in the vias. An LGA socket connects the front side vias of the backing plate to the LGA of signal vias on the back side of the mother board carrying the gate array or other IC. Thus, those signals that, in the absence of a backing plate, could be probed on the back side of the mother board can now still be probed at back side pads on the back side of the PCB backing plate, just as if that were the back side of the mother board.

Abstract: An assembly of two printed circuit boards (PCBs) mounted either perpendicular to or parallel to each other within a housing, each PCB bearing one or more low-profile high-density board-to-board commodity connectors providing equal numbers of electrical contacts. These commodity connectors mate to connectors permanently mounted on the daughterboard and backplane/sideplane. The assembly housing provides for semi-permanent attachment of the assembly to either the daughterboard or to the backplane/sideplane, as desired for a particular application. The housing may be made of conductive material in contact with earth ground to provide electromagnetic interference (EMI) shielding. Electrical continuity between the PCBs within the assembly is provided by signal conductors of specified electrical impedance and propagation delay.

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract: Disclosed is an apparatus and method for delivering power utilizing a multiplane power via matrix wherein the vias are each interconnected on each of the planes through which they pass such that a current flowing along any particular via, or via group, is free to either continue along its current path, or to move across any of the planes as a function of least resistance. The invention provides a system of vias for transferring power from any particular first plane to any desired second plane.

Abstract: A microelectronic package comprising a circuit carrier having a power chip, an integrated circuit means, and thermal conduction means for carrying heat from the microelectronic package is provided. The thermal conduction means includes a first heat dissipation back plate means associated with the power chip and a second heat dissipation back plate means associated with the integrated circuit means. The heat dissipation back plate means are electrically isolated from each other and have different heat dissipation capacity.

Abstract: Disclosed is a method of fabricating a microelectronic package, especially a microelectronic package having copper circuitization on a dielectric substrate. The method includes depositing copper on opposite surfaces of the package, and then depositing resist atop the copper. The resist is patterned, e.g., by photolithography or screening so that intended circuitization traces are covered by the resist. The exposed copper is etched, and the resist is stripped off of the unexposed copper. The process is characterized in that the etchant is upwardly sprayed onto a downwardly facing first surface of the package for half of the etching cycle, and then the package is rotated so that etchant is upwardly sprayed onto the downwardly facing second surface of the package.

Abstract: Disclosed is a method of reworking a circuit panel, and a reworked circuit panel structure. The method includes providing a conformal, polymeric, dielectric coating or coatings on the surface of the panel, providing conductive circuitization atop the conformal, polymeric, dielectric coating or coatings on the surface of the panel, and providing a top conformal, polymeric, dielectric coating atop the conductive circuitization layer. Also disclosed is a rerouted circuit panel having at least two surface features that are connected by a rerouted current lead. The current lead is formed of a dielectric encapsulated conductor electrically joining the two surface features. The dielectric encapsulated conductor structure includes a conformal, polymeric dielectric bottom layer adherent to a surface of the circuit board, with a provided conductor on the conformal, polymeric dielectric layer, and a conformal, polymeric dielectric layer provided atop the provided conductor.

Abstract: Disclosed is a multilayer circuit package having a buried thin film capacitor. The circuit package includes at least a power core, a ground core, a first signal core, a second signal core, and the integral, buried, thin film capacitor. The integral, buried, thin film capacitor serves to capacitively couple the first and second signal cores. Structurally, the first signal core includes at least one first wire that terminates in at least one first electrode, while the second signal core includes at least one second wire that terminates in at least one second electrode. At least a portion of the first electrode overlays at least a portion of the first electrode overlays at least a portion of the second electrode and is separated therefrom by a thin film of a dielectric material. The first electrode, the second electrode, and the thin film of dielectric material define the integral buried capacitor. The thin film capacitor is prepared by thin film methodology, with epitaxial deposition of the dielectric.