Patents by Inventor Richard Scott Burton
Richard Scott Burton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018216Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.Type: GrantFiled: June 24, 2019Date of Patent: May 25, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Publication number: 20200294993Abstract: An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shuji FUJIWARA, Richard Scott BURTON
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Patent number: 10692853Abstract: An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).Type: GrantFiled: September 14, 2015Date of Patent: June 23, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shuji Fujiwara, Richard Scott Burton
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Patent number: 10637468Abstract: An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.Type: GrantFiled: October 23, 2017Date of Patent: April 28, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Richard Scott Burton
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Publication number: 20190319087Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.Type: ApplicationFiled: June 24, 2019Publication date: October 17, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Patent number: 10411086Abstract: In accordance with an embodiment, a method of manufacturing an electrical component that may include a high voltage capacitor that includes providing a semiconductor material of a second conductivity type in which first doped region of a first conductivity type is formed. A plurality of doped regions of the first conductivity type and a plurality of doped regions of the second conductivity type are formed in the first doped region. A first p-n junction is formed between first doped regions of the first and second conductivity types and a second p-n junction is formed between second doped regions of the first and second conductivity types. A metallization system is formed above the doped regions so that capacitors are formed by a parallel connection of a first metal layer to a polysilicon layer and the first metal layer to a second metal layer.Type: GrantFiled: March 20, 2015Date of Patent: September 10, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Publication number: 20180240761Abstract: Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative system embodiment includes first and second integrated circuits. The first integrated circuit includes: a transmitter that produces a modulated carrier signal on a primary conductor; a first transfer conductor connected to a first connection terminal; and a first floating loop electromagnetically coupled to the primary conductor and to the transfer conductor to convey the modulated carrier. The second integrated circuit includes: a second transfer conductor connected to a second connection terminal, the second connection terminal being electrically connected to the first connection terminal; a receiver that demodulates the modulated carrier signal; and a second floating loop electromagnetically coupled to the second transfer conductor and to the receiver to convey the modulated carrier signal to the receiver.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Patent number: 10008457Abstract: Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative multi-module integrated circuit comprises: a transmitter in a first module, the transmitter providing a modulated carrier signal; a receiver in a second module demodulating the modulated carrier signal; and a galvanically isolated signaling path that includes: a first integrated resonator in the first module and a second integrated resonator in the second module, the first and second integrated resonators being resonantly coupled to convey the modulated carrier signal from the transmitter to the receiver.Type: GrantFiled: October 18, 2016Date of Patent: June 26, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Patent number: 9954523Abstract: An illustrative integrated circuit configured for galvanically isolated signaling includes a receiver having: a detector module coupled to receive a differential signal from terminals of a transformer secondary, the detector module responsively presenting an impedance that varies based on a magnitude of the differential signal; a biasing module that converts the detector module impedance to a response signal; and a comparator module that compares the response signal to a reference signal to obtain a detection signal indicative of oscillation in the differential signal.Type: GrantFiled: October 18, 2016Date of Patent: April 24, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Publication number: 20180109256Abstract: An illustrative integrated circuit configured for galvanically isolated signaling includes a receiver having: a detector module coupled to receive a differential signal from terminals of a transformer secondary, the detector module responsively presenting an impedance that varies based on a magnitude of the differential signal; a biasing module that converts the detector module impedance to a response signal; and a comparator module that compares the response signal to a reference signal to obtain a detection signal indicative of oscillation in the differential signal.Type: ApplicationFiled: October 18, 2016Publication date: April 19, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Publication number: 20180108621Abstract: Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative multi-module integrated circuit comprises: a transmitter in a first module, the transmitter providing a modulated carrier signal; a receiver in a second module demodulating the modulated carrier signal; and a galvanically isolated signaling path that includes: a first integrated resonator in the first module and a second integrated resonator in the second module, the first and second integrated resonators being resonantly coupled to convey the modulated carrier signal from the transmitter to the receiver.Type: ApplicationFiled: October 18, 2016Publication date: April 19, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Publication number: 20180109257Abstract: An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.Type: ApplicationFiled: October 23, 2017Publication date: April 19, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Publication number: 20170077083Abstract: An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shuji FUJIWARA, Richard Scott BURTON
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Publication number: 20150287774Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, a method includes forming a first electrically conductive structure over a first portion of the first layer of dielectric material and forming a second electrically conductive structure over a second portion of the first layer of dielectric material. A second layer of dielectric material is formed over the first electrically conductive structure and a third electrically conductive structure over the second layer of dielectric material, wherein the third electrically conductive structure is over portions of the first and second electrically conductive structures.Type: ApplicationFiled: March 20, 2015Publication date: October 8, 2015Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek