Patents by Inventor Richard Shirley
Richard Shirley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240250068Abstract: An integrated circuit device package includes a substrate, at least two integrated circuit dies mounted to the substrate, and a thermally conductive stiffener attached to the substrate to counteract warping of the substrate. The stiffener has a first portion in a thermally conductive relationship with a surface of a first integrated circuit die to provide a first heat dissipation mode for the first integrated circuit die, and has a second portion, different from the first portion, the second portion being configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die. The stiffener may be configured to expose a surface of the second integrated circuit die through an opening in the stiffener. A heat sink may be disposed in a thermally conductive relationship with the second integrated circuit die through the opening in the stiffener.Type: ApplicationFiled: January 22, 2024Publication date: July 25, 2024Inventors: Richard Graf, Alaba Bamido, Dwayne Richard Shirley, Wolfgang Sauter
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Patent number: 12021003Abstract: A semiconductor device package includes a semiconductor die having two largest dimensions that define a major plane, a packaging material enclosing the semiconductor die, a plurality of contacts on a first exterior surface of the semiconductor device package that is parallel to the major plane, the first exterior surface defining a bottom of the semiconductor device package, and a pedestal of semiconductor material above the semiconductor die in a thermally-conductive, electrically non-conductive relationship with the semiconductor die. The semiconductor material of the pedestal may be doped to provide electromagnetic shielding of the semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: June 25, 2024Assignee: Marvell Asia Pte, Ltd.Inventors: Han Gao, Ershad Ali, Shrinath Ramdas, Dwayne Richard Shirley, Roberto Coccioli
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Patent number: 11694971Abstract: Embodiments relate to a die package featuring a sputtered metal shield to reduce Electro-Magnetic Interference (EMI). According to a particular embodiment, a die featuring a top surface exposed by surrounding Molded Underfill (MUF) material, is subjected to metal sputtering. The resulting sputtered metal shield is in direct physical and thermal contact with the die, and is in electrical contact with a substrate supporting the die (e.g., to provide shield grounding). Specific embodiments may be particularly suited to reducing the EMI of a package containing an electro-optic die, to between 3-15 dB. The conformal nature and small thickness of the sputtered metal shield desirably conserves space and reduces package footprint. Direct physical contact between the shield and the die surface exposed by the MUF, enhances thermal communication (e.g., reducing junction temperature). According to certain embodiments, the sputtered metal shield comprises a stainless steel liner, copper, and a stainless steel coating.Type: GrantFiled: April 13, 2021Date of Patent: July 4, 2023Assignee: MARVELL ASIA PTE LTDInventors: Roberto Coccioli, Poorna Chander Ravva, Dwayne Richard Shirley, Jing Li, Shrinath Ramdas, Hassan Kobeissi, Shaohui Yong
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Publication number: 20230051507Abstract: A semiconductor device package includes a semiconductor die having two largest dimensions that define a major plane, a packaging material enclosing the semiconductor die, a plurality of contacts on a first exterior surface of the semiconductor device package that is parallel to the major plane, the first exterior surface defining a bottom of the semiconductor device package, and a pedestal of semiconductor material above the semiconductor die in a thermally-conductive, electrically non-conductive relationship with the semiconductor die. The semiconductor material of the pedestal may be doped to provide electromagnetic shielding of the semiconductor die.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Han Gao, Ershad Ali, Shrinath Ramdas, Dwayne Richard Shirley, Roberto Coccioli
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Publication number: 20220344297Abstract: A semiconductor package includes spread inhibiting structure to constrain the movement of viscous material during fabrication. In some embodiments, the spread inhibiting structure comprises a recess in an underside of a package lid overlying the die. According to other embodiments, the spread inhibiting structure comprises polymer disposed on the lid underside proximate to a side of the packaged die. According to still other embodiments, the spread inhibiting structure comprises a polymer disposed around the top of the die to serve as a dam and contain spreading. In some embodiments, the viscous material may be a Thermal Integration Material (TIM) in an uncured state, and the polymer may be the TIM in a cured state.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Choong Kooi CHEE, Dwayne Richard SHIRLEY, Han GAO
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Publication number: 20190197506Abstract: A system and method that enables merchants to settle credit card batches in real time. The system and method may be customized by individual merchants in a manner that allows merchants to be funded virtually instantaneously for credit card batches submitted via a real-time settlement process.Type: ApplicationFiled: September 12, 2018Publication date: June 27, 2019Inventors: Robert Jay McShirley, Kyle Taylor, Richard Shirley
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Patent number: 9793190Abstract: A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon layer. Another embodiment has a lid with a copper substrate and a native silicon oxide layer connected to the substrate by at least one intermediate layer. A method of providing a heat path through an integrated circuit package includes providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.Type: GrantFiled: March 11, 2015Date of Patent: October 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Dwayne Richard Shirley
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Patent number: 9768108Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.Type: GrantFiled: September 20, 2015Date of Patent: September 19, 2017Assignee: QUALCOMM IncorporatedInventors: Jie Fu, Chin-Kwan Kim, Manuel Aldrete, Milind Pravin Shah, Dwayne Richard Shirley
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Publication number: 20160247754Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.Type: ApplicationFiled: September 20, 2015Publication date: August 25, 2016Inventors: Jie FU, Chin-Kwan KIM, Manuel ALDRETE, Milind Pravin SHAH, Dwayne Richard SHIRLEY
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Publication number: 20160230123Abstract: This invention relates to compositions which are capable of sequestering calcium ions and are derived in part from renewable carbohydrate feedstocks. The calcium sequestering compositions are mixtures containing one or more hydroxycarboxylic acid salts, one or more oxoacid anion salts, and one or more citric acid salts.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventors: Tyler N. Smith, Richard Shirley
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Patent number: 9347024Abstract: This invention relates to compositions which are capable of sequestering calcium ions and are derived in part from renewable carbohydrate feedstocks. The calcium sequestering compositions are mixtures containing one or more hydroxycarboxylic acid salts, one or more oxoacid anion salts, and one or more citric acid salts.Type: GrantFiled: April 20, 2012Date of Patent: May 24, 2016Assignee: Rivertop Renewables, Inc.Inventors: Tyler N. Smith, Richard Shirley
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Patent number: 9190341Abstract: A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.Type: GrantFiled: June 5, 2012Date of Patent: November 17, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Dwayne Richard Shirley
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Publication number: 20150187677Abstract: A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon layer. Another embodiment has a lid with a copper substrate and a native silicon oxide layer connected to the substrate by at least one intermediate layer. A method of providing a heat path through an integrated circuit package includes providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventor: Dwayne Richard Shirley
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Publication number: 20130320517Abstract: A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: Texas Instruments IncorporatedInventor: Dwayne Richard Shirley
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Publication number: 20120295986Abstract: This invention relates to compositions which are capable of sequestering calcium ions and are derived in part from renewable carbohydrate feedstocks. The calcium sequestering compositions are mixtures containing one or more hydroxycarboxylic acid salts and one or more aluminum salts.Type: ApplicationFiled: April 20, 2012Publication date: November 22, 2012Inventors: Tyler N. Smith, Richard Shirley
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Publication number: 20120277141Abstract: This invention relates to compositions which are capable of sequestering calcium ions and are derived in part from renewable carbohydrate feedstocks. The calcium sequestering compositions are mixtures containing one or more hydroxycarboxylic acid salts, one or more oxoacid anion salts, and one or more citric acid salts.Type: ApplicationFiled: April 20, 2012Publication date: November 1, 2012Inventors: Tyler N. Smith, Richard Shirley