Patents by Inventor Richard Siegmund
Richard Siegmund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100169527Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: ApplicationFiled: March 8, 2010Publication date: July 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernard Charles Drerup, Richard Siegmund, JR., Barry Joe Wolford
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Patent number: 7707347Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: GrantFiled: January 14, 2009Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr., Barry Joe Wolford
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Publication number: 20090132743Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: ApplicationFiled: January 14, 2009Publication date: May 21, 2009Inventors: Bernard Charles Drerup, Richard Siegmund, JR., Barry Joe Wolford
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Patent number: 7526595Abstract: An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: GrantFiled: July 25, 2002Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr., Barry Joe Wolford
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Patent number: 7080011Abstract: Speech Label Accelerators (SLAs) are provided that comprise an indirect memory, atom value memory, and adder circuitry. Optionally, the SLAs also comprise an accumulator, a load/accumulate multiplexer (mux), and a control unit. There are a variety of different configurations for the adder circuitry, and a configuration can be selected based on speed, power, and area requirements. A number of techniques are provided that allow a system having an SLA to handle more dimensions, atoms, or both than the SLA was originally designed for. A “zig-zag” method is provided that speeds processing in a system when using more dimensions than the SLA was originally designed for. Generally, the kernels used by the SLA will be Gaussian and separable, but non-Gaussian kernels and partially separable kernels may also be used by the SLA.Type: GrantFiled: August 2, 2001Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Yoanna Baumgartner, Gary Dale Carpenter, Brian E. D. Kingsbury, Harry Printz, Richard Siegmund
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Patent number: 7003064Abstract: In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.Type: GrantFiled: January 7, 2002Date of Patent: February 21, 2006Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr.
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Patent number: 6819726Abstract: The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.Type: GrantFiled: December 7, 2000Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr.
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Publication number: 20040019721Abstract: An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: ApplicationFiled: July 25, 2002Publication date: January 29, 2004Applicant: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Barry Joe Wolford
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Publication number: 20030128789Abstract: In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund
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Publication number: 20020071510Abstract: The invention includes a dynamic phase alignment circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.Type: ApplicationFiled: December 7, 2000Publication date: June 13, 2002Applicant: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund
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Publication number: 20020049582Abstract: Speech Label Accelerators (SLAs) are provided that comprise an indirect memory, atom value memory, and adder circuitry. Optionally, the SLAs also comprise an accumulator, a load/accumulate multiplexer (mux), and a control unit. There are a variety of different configurations for the adder circuitry, and a configuration can be selected based on speed, power, and area requirements. A number of techniques are provided that allow a system having an SLA to handle more dimensions, atoms, or both than the SLA was originally designed for. A “zig-zag” method is provided that speeds processing in a system when using more dimensions than the SLA was originally designed for. Generally, the kernels used by the SLA will be Gaussian and separable, but non-Gaussian kernels and partially separable kernels may also be used by the SLA.Type: ApplicationFiled: August 2, 2001Publication date: April 25, 2002Applicant: International Business Machines CorporationInventors: Yoanna Baumgartner, Gary Dale Carpenter, Brian E.D. Kingsbury, Harry Printz, Richard Siegmund
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Patent number: 5898885Abstract: A method and system for executing a non-native stack-based instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of executing a set of non-native stack-access instructions is provided which includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native stack-access instructions, and part of the system memory is utilized as a stack. The instruction set convertor is utilized to convert the non-native stack-access instructions to a set of native instructions. When encountering a block of non-native stack-access instructions which include paired push and pop stack operations, the instruction set convertor produces a set of native instructions that ignores paired push and pop stack operations and retains all relevant number values in general purpose registers.Type: GrantFiled: March 31, 1997Date of Patent: April 27, 1999Assignee: International Business Machines CorporationInventors: John Edward Dickol, Bernard Charles Drerup, Richard Siegmund, Jr.