Abstract: An integrated circuit having Radio Frequency Identification components and circuitry used for authentication is discussed. The RFID components and circuitry include two or more coils and corresponding electrical circuits that are tuned to use two or more different resonant frequencies including: a first resonant RF used for power generation and a second resonant RF used for data communication. The integrated circuit contains a unique signature that is used for the authentication with two or more aspects including i) a first aspect that is a programmed password in a memory embedded on the integrated circuit, and ii) a second aspect that is a unique, randomly generated code based upon a physical characteristic of the integrated circuit.

Abstract: Manufacturing integrated circuits is discussed with steps as follows. Creating a wafer with a plurality of dies, where each die contains its own integrated circuit. Fabricating multiple instances of TAP circuitry located in a margin between dies of the wafer. Fabricating on the wafer one row of test pads and power pads per group of dies on the wafer, where the row of test pads and power pads is electrically connected and shared among all of the dies in the group. The test and power pads connect to a chain of TAP circuitry in order to supply operating power as well as testing data to verify the integrity of each die in that group of dies. Singulating the dies to create each instance of the integrated circuit, and during the singulation process, the TAP circuitry located in the margin between the dies is destroyed.

Abstract: An integrated circuit having Radio Frequency Identification components and circuitry used for authentication is discussed. The RFID components and circuitry include two or more coils and corresponding electrical circuits that are tuned to use two or more different resonant frequencies including: a first resonant RF used for power generation and a second resonant RF used for data communication. The integrated circuit contains a unique signature that is used for the authentication with two or more aspects including i) a first aspect that is a programmed password in a memory embedded on the integrated circuit, and ii) a second aspect that is a unique, randomly generated code based upon a physical characteristic of the integrated circuit.

Abstract: Manufacturing integrated circuits is discussed with steps as follows. Creating a wafer with a plurality of dies, where each die contains its own integrated circuit. Fabricating multiple instances of TAP circuitry located in a margin between dies of the wafer. Fabricating on the wafer one row of test pads and power pads per group of dies on the wafer, where the row of test pads and power pads is electrically connected and shared among all of the dies in the group. The test and power pads connect to a chain of TAP circuitry in order to supply operating power as well as testing data to verify the integrity of each die in that group of dies. Singulating the dies to create each instance of the integrated circuit, and during the singulation process, the TAP circuitry located in the margin between the dies is destroyed.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: The present invention is directed to a method and system for improved motion compensated noise reduction. The system uses a temporal noise reduction filter to remove noise from the current input field and pass it through a de-interlacer to produce a noise reduced full output frame. The temporal noise reduction filter reduces noise in the present field by blending it with a predicted (motion compensated) field determined from the immediately preceding full output frame. In accordance with the invention where the current input field is for time or sequence n, the motion compensated field can be determined from the output frame corresponding to time or sequence n?1. In addition, the motion compensated field can be predicted using motion estimation and motion compensation using the current input field and the previous output frame. By using the previous de-interlaced frame which includes the information for both field polarities, the vertical resolution of the motion estimation process can be improved.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types The ordered requests are then delivered to memory Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which decodes an ATSC encoded image and employs a downconversion process to produce a standard definition video signal. The video decoder includes a frequency-domain filter to reduce the resolution of the ATSC encoded signal. The video decoder downconversion system also includes a formatting section having vertical and horizontal filters, as well as resampling processing, to format the decoded and downconverted video image for a particular display and aspect ratio. The decoder senses the display format of the encoded video signal and changes the processing provided by the decoder to produce a standard definition output signal regardless of the display format of the encoded input signal. The system also includes a format converter which may be programmed to use a plurality of methods to convert the aspect ratio of the input signal for display on a display device having a different aspect ratio.

Abstract: A video monitor including circuitry that provides information regarding characteristics of the monitor to an external video source. The circuitry may be a register that holds data from which the aspect ratio and resolution of the display may be derived.

Abstract: A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP@HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP@ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP@HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP@HL signal when the decoder is operated in the second mode.

Abstract: A video memory system for storing ATSC video image data is configured as three channels, each channel having two banks and each bank including a plurality of memory rows. The exemplary memory system includes a buffer area for holding bit-stream data and six field buffer areas. The field buffer areas are arranged in pairs to form a three frame buffer areas, such that the buffer areas for the two fields in a given frame are allocated in respectively different banks. The video memory system includes an output memory controller which receives macroblocks of decoded image data and divides the received macroblocks into respective upper and lower half-macroblocks, the upper half-macroblock being stored in one field buffer of the frame and the lower half-macroblock being stored in the other field buffer of the frame.

Abstract: Apparatus and method for determining the lengths of a plurality of variable length encoded data values included in a data stream within a single clock cycle. The apparatus includes a shifter for receiving the data stream. The shifter is responsive to a shift control signal for transmitting a subset of the plurality of variable length encoded data values. A first length decoding mechanism is coupled to receive the subset of the plurality of encoded data values. The first length decoding mechanism performs a first decoding operation to determine the length of a first one of the encoded data values in the subset. A second length decoding mechanism is also coupled to receive the subset of the plurality of encoded data values. The second length decoding mechanism performs a second decoding operation to individually determine the length of a second one of the encoded data values in the subset. The second encoded data value immediately follows the first encoded data value in the subset.