Abstract: Layer processing for pharmaceuticals, and related systems, methods, and articles are generally described. In some embodiments, ingestible pharmaceutical products (e.g., tablets) can be formed by processing one or more layers containing a pharmaceutically active composition. For example, at least one layer containing a pharmaceutically active composition can be manipulated (e.g., folded, rolled, stacked, etc.) such that the average thickness of the product formed by the manipulation is at least about two times the average thickness of the portions of the layer(s) used to form the product. In some embodiments, after the layer is manipulated, it can be processed (e.g., cut, coated, etc.) to form a final product such as, for example, a tablet.

Abstract: Layer processing for pharmaceuticals, and related systems, methods, and articles are generally described. In some embodiments, ingestible pharmaceutical products (e.g., tablets) can be formed by processing one or more layers containing a pharmaceutically active composition. For example, at least one layer containing a pharmaceutically active composition can be manipulated (e.g., folded, rolled, stacked, etc.) such that the average thickness of the product formed by the manipulation is at least about two times the average thickness of the portions of the layer(s) used to form the product. In some embodiments, after the layer is manipulated, it can be processed (e.g., cut, coated, etc.) to form a final product such as, for example, a tablet.

Abstract: A pill organizer and dispenser enables a supply of medicinal pills to be taken over a pre-selected period of time by placement on a grid which has slots representing days of the week for containment of pills in respective receptacles which may then be dispensed by tilting the grid to cause the pills to slide between the slots for collection.

Abstract: An encoder providing on a single terminal of a circuit package a composite serial data stream containing both stored data bits of a multistage binary memory and a clock signal needed for decoding the data. A parallel to serial converter serially shifts the stored binary data bits to an output thereof in response to clock pulses of an internal clock, and a logic circuit responsive to both the internal clock and the serial binary data from the converter generates first, second and third signals of amplitudes discernibly different from one another respectively in response to 1-state data bits, 0-state data bits and the termination of clock pulses. Two fixed inputs to the converter respectively provide a 1-state start bit at the beginning of the set of data bits and a 0-state stop bit at the end of the set of data bits for purposes of decoding. An amplitude discriminating decoder uses the periodic third signals and the start and stop bits to decode the serial data.