Patents by Inventor Richard Slobodnik
Richard Slobodnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11568926Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.Type: GrantFiled: November 23, 2020Date of Patent: January 31, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
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Patent number: 11280832Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.Type: GrantFiled: September 6, 2020Date of Patent: March 22, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Frank David Frederick, Richard Slobodnik
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Publication number: 20220074988Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.Type: ApplicationFiled: September 6, 2020Publication date: March 10, 2022Inventors: Andy Wangkun Chen, Frank David Frederick, Richard Slobodnik
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Publication number: 20210074353Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Inventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
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Patent number: 10847211Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.Type: GrantFiled: April 18, 2018Date of Patent: November 24, 2020Assignee: Arm LimitedInventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
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Publication number: 20190325947Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Andy Wangkun Chen, Teresa Louise McLaurin, Frank David Frederick, Richard Slobodnik, Yew Keong Chong
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Patent number: 10222418Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.Type: GrantFiled: December 2, 2016Date of Patent: March 5, 2019Assignee: ARM LimitedInventors: Yew Keong Chong, Teresa Louise Mclaurin, Richard Slobodnik, Frank David Frederick, Kartikey Jani
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Publication number: 20180156866Abstract: Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.Type: ApplicationFiled: December 2, 2016Publication date: June 7, 2018Inventors: Yew Keong Chong, Teresa Louise Mclaurin, Richard Slobodnik, Frank David Frederick, Kartikey Jani
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Patent number: 7434119Abstract: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.Type: GrantFiled: March 7, 2005Date of Patent: October 7, 2008Assignee: ARM LimitedInventors: Richard Slobodnik, Frank David Frederick
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Patent number: 7308623Abstract: An integrated circuit and method for testing memory on that integrated circuit includes processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided for executing test events in order to seek to detect any memory defects in the number of memory units. The controller includes a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the controller is then operable, following the single programming operation, to execute the sequence of test events.Type: GrantFiled: March 10, 2005Date of Patent: December 11, 2007Assignee: ARM LimitedInventors: Richard Slobodnik, Paul Stanley Hughes, Frank David Frederick, Brandon Michael Backlund
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Patent number: 7293212Abstract: A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units.Type: GrantFiled: March 22, 2005Date of Patent: November 6, 2007Assignee: ARM LimtedInventors: Conrado Blasco Allue, Stephen John Hill, Richard Slobodnik
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Patent number: 7269766Abstract: A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.Type: GrantFiled: December 26, 2001Date of Patent: September 11, 2007Assignee: ARM LimitedInventors: Richard Slobodnik, Stephen John Hill, Gerard Richard Williams
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Publication number: 20060218449Abstract: A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units.Type: ApplicationFiled: March 22, 2005Publication date: September 28, 2006Applicant: ARM LimitedInventors: Conrado Blasco Allue, Stephen Hill, Richard Slobodnik
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Publication number: 20060212764Abstract: An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided which is operable to execute test events in order to seek to detect any memory defects in the number of memory units. The memory test controller comprises a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the memory test controller is then operable, following the single programming operation, to execute the sequence of test events.Type: ApplicationFiled: March 10, 2005Publication date: September 21, 2006Applicant: ARM LimitedInventors: Richard Slobodnik, Paul Hughes, Frank Frederick, Brandon Backlund
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Publication number: 20060200713Abstract: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.Type: ApplicationFiled: March 7, 2005Publication date: September 7, 2006Applicant: ARM LimitedInventors: Richard Slobodnik, Frank Frederick
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Patent number: 7062689Abstract: A self-test controller for memory devices is provided with an integrated circuit. The self-test controller produces physical memory address values for driving desired memory tests. A mapping circuit serves to map these physical memory address signals to logical memory address signals as required by the particular memory devices. In this way a generic self-test controller may be provided that is able to drive tests within multiple different memory devices by providing a relatively simple mapping circuit.Type: GrantFiled: December 20, 2001Date of Patent: June 13, 2006Assignee: ARM LimitedInventor: Richard Slobodnik
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Patent number: 7053675Abstract: A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way.Type: GrantFiled: July 25, 2003Date of Patent: May 30, 2006Assignee: ARM LimitedInventors: Richard Slobodnik, Gerard Richard Williams, Mark Allen Silla
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Publication number: 20050017763Abstract: A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way.Type: ApplicationFiled: July 25, 2003Publication date: January 27, 2005Applicant: ARM LIMITEDInventors: Richard Slobodnik, Gerard Williams, Mark Silla
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Publication number: 20030167426Abstract: A self-test controller 10 for memory devices 6, 8 is provided with an integrated circuit 2. The self-test controller 10 produces physical memory address values Xaddr, Yaddr for driving desired memory tests. A mapping circuit 24, 26 serves to map these physical memory address signals to logical memory address signals LA[8:0] as required by the particular memory devices 6, 8. In this way a generic self-test controller may be provided that is able to drive tests within multiple different memory devices 6, 8 by providing a relatively simple mapping circuit 24, 26.Type: ApplicationFiled: December 20, 2001Publication date: September 4, 2003Inventor: Richard Slobodnik
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Publication number: 20030120985Abstract: A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.Type: ApplicationFiled: December 26, 2001Publication date: June 26, 2003Inventors: Richard Slobodnik, Stephen John Hill, Gerard Richard Williams