Abstract: Described embodiments provide for a memory system having a transparent source bias (TSB) circuit. A monitor in the memory system monitors a process, temperature, and/or a leakage current of the memory. The system determines whether at least one of the monitored process, temperature, and leakage current reaches a corresponding threshold. The threshold is set based on a power budget of the memory. If the corresponding threshold is reached, the TSB is disabled and the memory operates at a relatively high speed. If the corresponding threshold is not reached, the TSB is enabled and the memory operates at a relatively law speed.

Abstract: A ROM-based multiple match system and method for producing a match signal in an addressable memory system are described. In various embodiments of the present invention, a ROM is used to generate single match and multiple match signals, as well as encoded address signals indicating a matching location(s) within the memory. The ROM is provided with specific entries in the form of a lookup table, which are used to signal combinational logic that provides an output to the system. In certain embodiments of the invention, the ROM may be divided into hierarchical sub-blocks that provide more efficient processing of a digital data related to matching of an input word, improved usage of space within a chip or better scalability across the multiple match system.

Abstract: A ROM-based multiple match system and method for producing a match signal in an addressable memory system are described. In various embodiments of the present invention, a ROM is used to generate single match and multiple match signals, as well as encoded address signals indicating a matching location(s) within the memory. The ROM is provided with specific entries in the form of a lookup table, which are used to signal combinational logic that provides an output to the system. In certain embodiments of the invention, the ROM may be divided into hierarchical sub-blocks that provide more efficient processing of a digital data related to matching of an input word, improved usage of space within a chip or better scalability across the multiple match system.

Abstract: Apparatus and methods for an improved priority encoder using only static circuit components. Features and aspects hereof rely exclusively on static logic circuits exclusive ROM and other memory structures as relied on in prior structures. The exemplary static circuit structures relied upon in accordance with features and aspects hereof are less susceptible to leakage current and other issues common in high density integrated circuit applications. Thus, features and aspects hereof avoid use of ROM and other similar memory devices in favor of digital encoders comprised of static logic circuits cascaded through multiplexers to provide priority encoding in digital circuit applications coupling multiple devices to a shared, common bus structure.