Abstract: System and method for synchronizing clocks and maintaining packet timing relationships in a wireless communications system. A preferred embodiment further comprises periodically synchronizing local clocks at a transmitter and a receiver to a clock reference, adding a timestamp to each application packet at a transmitter of a wireless network, setting the timestamp to a value of a local time at the transmitter plus a link delay, buffering a received packet at a receiver, and releasing the buffered packet to an application level when a value of a local time at the receiver equals the timestamp value in the packet. This can help to ensure that the timing relationships between data packets present at a transmitter is maintained at a receiver, regardless of transport delays (waiting, transmission and processing) incurred by the data packets.

Abstract: In a PCI-interface device (20), the present invention autonomously outputs video data (440) from data packets (426) including a header portion (428) and a video data portion (430). The invention receives the data packets (440) in a data packet transfer device (20), and associates an address with a plurality of address fields (428, 418) within the data packets (426). Decoding of the header portion (428) and an address segment within the video data portion occurs to determine whether the header portion (428) comprises a vertical synch signal (407). Also, the address segment of the video data portion is decoded to determine whether the video data portion comprises a horizontal synch signal (409). The invention separates the header portion from the video data portion and then flows the video data portion (430) into a zoom port.

Abstract: A method and system for autonomously operation a PCI-serial bus interface device (20) in an autonomous mode includes directing circuitry (370) for directing an autonomous boot mode select signal to the data transfer device. Instructions configure registers (36, 38) associated with the data transfer device for autonomous operation of a data transfer device. The directing circuit (370) associates with the data packet transfer device for transferring data to at least one program control list (456) for operating said data packet transfer device in an autonomous mode.

Abstract: A packet control list (456) controls the transfer of data packets between at least one source location (452) and at least one destination location (460) each associated with a data packet transfer device (20). Packet control list (456) associates a plurality of data packet transfer control instructions (454) in a sequential list (466) including a plurality of logical functions (472) for controlling logical operations relating to the transfer of data packets from at least one source location (452) to at least one destination location (460). Instructions (486) control the operation of data packet transfer device (20) according to instructions (486).

Abstract: Register write circuitry (250) writes to a plurality of data register bits (276) using a single register write operation by storing both designated address bits (276) and an address field (274) for addressing a predetermined data register. The designation address bits (276) designate predetermined bits (A.sub.4,A.sub.2,A.sub.2,A.sub.1) within data register (76) to which data was to be written. Writing data (274) only to predetermined bits (276) in a register write operation uses a single write enable command (272) in a programmable and selectable manner without performing a read-modify-write or requiring the storage of a bit image of the register.

Abstract: In a PCI-interface device (20), assigning highest DMA channel (74) priority is based on the DMA channel number associated with the data transfer currently active on the physical media interface. The present invention supplies this priority information relating to the currently active data packet being transferred to the DMA arbitration logic (348) and continues to service the current DMA channel until a predetermined boundary condition exists. The method and system (300) shift DMA channel execution to this highest priority DMA channel upon determining the occurrence of the boundary condition.

Abstract: DMA channel receive packet comparator logic (74) of PCI-interface ASIC (20) assigns a data packet (106) through a data communications channel and includes DMA channel comparator logic (110) for receiving at least a portion of an incoming data packet (108) in data comparison circuit (110). Data packet comparison circuit (120) compares at least a portion of incoming data packet (108) to a predetermined match data set (122). Packet portion (108) and the match data set (122) form programmably varying data fields (WD0, WD1) corresponding to at least one data communications channel (117, 119,121, 123). In the event of a predetermined correspondence between portion (108) and match data set (122), a channel select signal (117, 119, 121, 123) goes to a channel priority encoder (125).