Abstract: The disclosure is an improved Random Access Memory (RAM) integrated circuit chip. More specifically, enhancement - depletion mode field effect transistor technology is employed to provide a solid state memory having improved "reading" and "writing" capability.A pair of N-channel depletion mode devices are used to initialize the bit lines before the start of the next read or write cycle. These devices are switched to a high conductive state resulting in a rapid initialization of the bit lines. A sense latch circuit incorporating enhancement and depletion mode devices is used to detect and latch a small differential signal on the bit lines. The state of the sense latch is isolated from and does not affect the bit line voltages at any time during the memory cycle. M pairs of N-channel depletion mode devices are provided. One pair for each of B/S lines. M sense latch circuits are provided. One for each pair of B/S lines.