Abstract: A power regulator circuit automatically disables an internal pass transistor when a detection circuit detects the presence of an external pass device. The internal pass transistor is made in an integrated circuit along with a detection circuit and a switch for disabling the internal pass transistor. The detection circuit detects a presence of an external pass device external to the integrated circuit. The switch automatically disables the internal pass transistor when the detection circuit detects the presence of the external pass device. The detection circuit has a comparator for comparing a signal on an outside connection of the integrated circuit and a latch to operate the switch. The comparator compares a voltage on an outside connection of the integrated circuit against a reference after power up of the regulator and can delay operation of the comparison until a predetermined time after power up. An integrated circuit can contain the power regulator circuit and the internal pass transistor.

Abstract: A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.

Abstract: A power regulator circuit automatically disables an internal pass transistor when a detection circuit detects the presence of an external pass device. The internal pass transistor is made in an integrated circuit along with a detection circuit and a switch for disabling the internal pass transistor. The detection circuit detects a presence of an external pass device external to the integrated circuit. The switch automatically disables the internal pass transistor when the detection circuit detects the presence of the external pass device. The detection circuit has a comparator for comparing a signal on an outside connection of the integrated circuit and a latch to operate the switch. The comparator compares a voltage on an outside connection of the integrated circuit against a reference after power up of the regulator and can delay operation of the comparison until a predetermined time after power up. An integrated circuit can contain the power regulator circuit and the internal pass transistor.

Abstract: A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.

Abstract: A dual access peripheral interface uses a shared data bus (16) for communication with dual master units (30,32) coupled to a common peripheral device (34). Each master control unit provides a shared subset of control bits to a logic configuration block (48), which combines the control bits in a logic operation to present to the slave peripheral unit (34). The logic configuration block (48) is configured by configuration bits accessible by only one of the master units (30). In this way, both of the master units can access the peripheral at the same time with the logic of the logic configuration block determining the ultimate control of the peripheral.

Abstract: A dual access peripheral interface uses a shared data bus (16) for communication with dual master units (30,32) coupled to a common peripheral device (34). Each master control unit provides a shared subset of control bits to a logic configuration block (48), which combines the control bits in a logic operation to present to the slave peripheral unit (34). The logic configuration block (48) is configured by configuration bits accessible by only one of the master units (30). In this way, both of the master units can access the peripheral at the same time with the logic of the logic configuration block determining the ultimate control of the peripheral.