Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: A voltage regulator includes first and second bias circuits, a transistor, and a load prediction circuit. The transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode for providing a regulated output voltage, and a control electrode. The first biasing circuit is for providing a first bias voltage to the control electrode of the transistor in response to a feedback signal generated from the regulated output voltage. The second biasing circuit is for providing a second bias voltage to the control electrode of the transistor in response to a control signal. The load current prediction circuit is coupled to the second biasing circuit. The load prediction circuit is for providing the control signal to the second biasing circuit in response to determining that a load current at the second current electrode is expected to increase.

Abstract: A voltage regulator includes first and second bias circuits, a transistor, and a load prediction circuit. The transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode for providing a regulated output voltage, and a control electrode. The first biasing circuit is for providing a first bias voltage to the control electrode of the transistor in response to a feedback signal generated from the regulated output voltage. The second biasing circuit is for providing a second bias voltage to the control electrode of the transistor in response to a control signal. The load current prediction circuit is coupled to the second biasing circuit. The load prediction circuit is for providing the control signal to the second biasing circuit in response to determining that a load current at the second current electrode is expected to increase.

Abstract: A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.

Abstract: A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Reducing output voltage ripple of power supplies. In some embodiments, an electronic circuit may include a first node configured to receive an input signal proportional to an output voltage produced by a power supply, a second node configured to receive a reference voltage configured to alternate between two voltage values during operation of the power supply, and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage. In other embodiments, a method may include turning on a power supply in response to a falling ripple being smaller than a first reference voltage value, and turning off the power supply in response to a rising ripple being greater than a second reference voltage value, where the second reference voltage value is smaller than the first reference voltage value.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Reducing output voltage ripple of power supplies. In some embodiments, an electronic circuit may include a first node configured to receive an input signal proportional to an output voltage produced by a power supply, a second node configured to receive a reference voltage configured to alternate between two voltage values during operation of the power supply, and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage. In other embodiments, a method may include turning on a power supply in response to a falling ripple being smaller than a first reference voltage value, and turning off the power supply in response to a rising ripple being greater than a second reference voltage value, where the second reference voltage value is smaller than the first reference voltage value.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.

Abstract: Schmitt trigger with rail-to-rail or near rail-to-rail hysteresis. In some embodiments, a method includes switching an output of a Schmitt trigger from a first logic state to a second state in response to an input meeting a threshold, where the threshold is applied to a first transistor of a first doping type and the input is applied to a second transistor of the first doping type, the first and second transistors operably coupled to each other through a current mirror of a second doping type. The first doping type may be an n-type, the second doping type may be a p-type, and the threshold may be a rising threshold having a value within 10% of a supply voltage. Alternatively, the first doping type may be a p-type, the second doping type may be an n-type, and the threshold may be a falling threshold having a value within 10% of ground.

Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.

Abstract: A clamping circuit of a DC/DC regulator includes a reference current generator to generate a reference current. The reference current can be based upon a specified maximum voltage across a bootstrap capacitor of the DC/DC regulator. The clamping circuit also includes a current generator that generates a current based on the voltage across the bootstrap capacitor. The current generated by the current generator is compared to the generated reference current. Based on the comparison, the voltage across the bootstrap capacitor is regulated. By regulating the voltage across the bootstrap capacitor based on current, rather than based directly on the voltage across the capacitor, the design of the clamping circuit is simplified compared to voltage-based implementations.

Abstract: A clamping circuit of a DC/DC regulator includes a reference current generator to generate a reference current. The reference current can be based upon a specified maximum voltage across a bootstrap capacitor of the DC/DC regulator. The clamping circuit also includes a current generator that generates a current based on the voltage across the bootstrap capacitor. The current generated by the current generator is compared to the generated reference current. Based on the comparison, the voltage across the bootstrap capacitor is regulated. By regulating the voltage across the bootstrap capacitor based on current, rather than based directly on the voltage across the capacitor, the design of the clamping circuit is simplified compared to voltage-based implementations.