Patents by Inventor Richard Unda
Richard Unda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150302335Abstract: A system and method for evaluating leadership abilities and identifying leadership talent among users and organizations in a social network, and to compare the leadership abilities of a user to the leadership abilities of other users or categories of users in a social network.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Inventor: Richard Unda
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Patent number: 8299503Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: GrantFiled: March 31, 2010Date of Patent: October 30, 2012Assignee: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Patent number: 7768037Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: GrantFiled: February 2, 2007Date of Patent: August 3, 2010Assignee: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Publication number: 20100187574Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: ApplicationFiled: March 31, 2010Publication date: July 29, 2010Applicant: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Patent number: 7341891Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: GrantFiled: October 31, 2003Date of Patent: March 11, 2008Assignee: Broadcom CorporationInventors: Manolito M Catalasan, Vafa J Rakshani, Edmund H Spittles, Tim Sippel, Richard Unda
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Publication number: 20070131966Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: ApplicationFiled: February 2, 2007Publication date: June 14, 2007Applicant: Broadcom CorporationInventors: Manolito Catalasan, Vafa Rakshani, Edmund Spittles, Tim Sippel, Richard Unda
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Patent number: 7078936Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.Type: GrantFiled: October 31, 2003Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Patent number: 6933547Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.Type: GrantFiled: October 31, 2003Date of Patent: August 23, 2005Assignee: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Publication number: 20040251472Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: ApplicationFiled: October 31, 2003Publication date: December 16, 2004Applicant: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Publication number: 20040251501Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.Type: ApplicationFiled: October 31, 2003Publication date: December 16, 2004Applicant: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Publication number: 20040253778Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.Type: ApplicationFiled: October 31, 2003Publication date: December 16, 2004Applicant: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda
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Publication number: 20040251470Abstract: A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit comprises a memory cell, a register and a control circuit. The memory cell has a first metal interconnect structure that traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is coupled to one of the first and second supply potentials, a second metal interconnect structure that traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is coupled to the other one of the first and second supply potentials, and an output, wherein a state of the output is programmable by altering any one of the plurality of metal layers or any one of a plurality of via layers. The register has a data input, a data output and control inputs. The control circuit is coupled to the control inputs of the register.Type: ApplicationFiled: October 31, 2003Publication date: December 16, 2004Applicant: Broadcom CorporationInventors: Manolito M. Catalasan, Vafa J. Rakshani, Edmund H. Spittles, Tim Sippel, Richard Unda