Abstract: In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC comprises an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

Abstract: Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order queue, and issuing transactions not tracked by the out-of-order queue.

Abstract: In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”).

Abstract: Circuitry for use with a general purpose performance counter (“GPPC”) connected to a bus carrying a plurality of encoded state coverage signals indicative of test coverage in a logic design, wherein the circuitry is operable to decode and capture the encoded coverage information. A selection circuit associated with the GPPC is operable to select the encoded state coverage signals from a multi-bit event signal on the bus. A line decoder coupled to the selection circuit decodes the encoded state coverage signals into N one-hot signals, which are asserted based on coverage of corresponding states during test. A capture circuit is operable to capture the N one-hot signals for further processing.

Abstract: A controller arrangement for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal. A bus clock synchronizer controller portion is operable to generate a set of clock relationship control signals, at least a portion of which signals are used in generating a set of bus domain synchronizer control signals towards bus-to-core and core-to-bus synchronizers. A core clock synchronizer controller portion is provided for generating a set of core domain synchronizer control signals towards the synchronizers. The core clock synchronizer controller portion is operable responsive to the clock relationship control signals as well as configuration information signals indicative of different skew tolerances and latency values associated with the clock signals.

Abstract: One method combines a slow data stream with one or more fast data streams into a single fast data stream, including: processing queued transactions of the fast data streams into the single fast data stream; determining when there are no queued transactions of the fast data streams; determining existence of a transaction from the slow data stream; if the transaction has data packets, inserting the transaction into the single fast data stream when there are no queued transactions; and if the transaction has no data packets, inserting the transaction into the single fast data stream. Systems are also disclosed to combine a slow data stream with one or more fast data streams to form a single fast data stream.

Abstract: A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal, the core and bus clock signals having a ratio of N core clock cycles to M bus clock cycles, where N/M≧1. A first synchronizer is provided for synchronizing data transfer from a core clock domain logic block to a bus clock domain logic block. A second synchronizer is operable to synchronize data transfer from the bus clock domain logic block to the core clock domain logic block. Control means are included for controlling the first and second synchronizers, the control means operating responsive at least in part to configuration means that is configurable based on skew tolerance and latency parameters.

Abstract: A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetween. A bus clock synchronizer controller operable in the bus clock domain includes circuitry for generating a set of inter-controller clock relationship control signals, which are provided to a core clock synchronizer controller. Responsive to the inter-controller clock relationship control signals, circuitry in the core clock synchronizer controller is operable to synchronize the core clock signal's cycle and sequence information relative to the bus clock signal.

Abstract: Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.

Abstract: A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector disposed in communication with the phase detector is operable to generate a skew state signal which tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew state signal by generating at least one control signal to compensate for the skew between the first clock signal and the second clock signal.

Abstract: A system and method for effectuating the transfer of data blocks having intervals across a clock boundary between a first clock domain and a second clock domain. A first circuit portion provides the data blocks to a second circuit portion. A synchronizer controller disposed between the first and second clock domains provides at least one dead cycle control signal to the second circuit portion, which is indicative of the location of at least one dead cycle between the first and second clock signals. Control logic associated with the second circuit portion generates data transfer control signals responsive to the at least one dead cycle control signal in order to control the second circuit portion so that the data blocks may be transmitted as contiguous data blocks relative to the at least one dead cycle.

Abstract: Disclosed are systems and methods for logging errors comprising at least one register for storing header packet information, a controller operable to determine if a received packet of one or more packets forming an information communication comprises a header packet and to store the header packet in said at least one register, and error logging circuitry coupled to the register operable to create an error log entry using header information retrieved from the register when an error is detected with respect to any of the one or more packets of the information communication.

Abstract: A system and method for maintaining a stable synchronization state in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a first circuit portion generates a load signal indicative of a known acceptable state for which a cycle can be loaded. A second circuit portion is in communication with the first circuit portion in order to generate a lock signal indicative of a tolerable tracked skew between a first clock signal of the first clock domain and a second clock signal of the second clock domain. A third circuit portion, responsive to the load signal, the lock signal and a zero skew point indicator, generates a synchronization stable state signal indicative of locking between the first clock signal and the second clock signal.

Abstract: A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The phase detector includes a series of flip flops disposed in parallel that sample the second clock signal with both a rising edge of the first clock signal and a falling edge of the first clock signal. By tracking movement in one-to-zero or zero-to-one transitions in the sampled clock signals, the phase detector is operable to determine the phase difference between the first and second clock signals.

Abstract: A system and method using a synchronizer circuit for effectuating data transfer across a clock domain boundary between a first clock domain and a second clock domain, wherein the first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. The first and second clock signals have a ratio of N first clock cycles to (N-1) second clock cycles. A first circuit portion operates to transfer (N-1) data bits, based on which clock cycle of the first clock signal has an extra data bit, out of N data bits across the clock boundary on a first data path of the synchronizer output. A second circuit portion operates to transfer the remaining extra data bit on a second data path of the synchronizer's output.

Abstract: An embodiment of this invention provides a system and method for indicating the orientation of a packaged IC in a socket. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a socket hole on the socket. When the orientation of the IC package in the socket is correct, the other lead of the LED is connected to a ground path on the packaged IC. As a result, the LED is activated indicating the orientation of the packaged IC is correct.

Abstract: A SYNC pulse compensation and regeneration apparatus and method for use with a high skew tolerant, low latency clock synchronizer controller utilized for synchronizing data transfer operations between two circuit portions across a clock domain boundary. A primary clock signal is operable to clock a first circuit portion and a secondary clock signal, generated from the primary clock signal, is operable to clock a second circuit portion. A SYNC pulse signal is generated based on coincident rising edges of the primary and secondary clock signals. A sampling compensation circuit is operable to condition the SYNC pulse signal by inserting a logic high pulse when the SYNC pulse is lost, or by removing duplicate SYNC pulses when necessary. A jitter cycle delay compensation circuit coupled to the sampling compensation circuit is operable to stage the SYNC pulse through a series of delay registers to compensate for clock skew when the SYNC pulse jumps ahead or behind a clock cycle.

Abstract: A system and method for synchronizing data transfer operations between two circuit portions across a clock domain boundary. A primary clock signal is operable to clock a first circuit portion and a secondary clock signal, generated from the primary clock signal, is operable to clock a second circuit portion. A SYNC pulse signal is generated based on coincident rising edges of the primary and secondary clock signals. A clock synchronizer controller is operable to generate a plurality of control signals based on the SYNC pulse signal for actuating data transfer circuitry disposed between the first and second circuit portions. A SYNC adjuster portion included in the clock synchronizer controller is operable to re-position the SYNC pulse signal by redefining a new coincident rising edge with respect to the primary and secondary clock signals based on a clock skew relative to each other.

Abstract: The coherent ordering queue in a processing agent chip in a multi-node processor system is designed so as to permit maximum flexibility with the various write operations of different processors, while decreasing the queue depth and increasing queue width for increased efficiency in searching and processing the queue.

Abstract: A processing system is provided which includes circuitry for generating memory requests at a first clock rate. Input queuing circuitry which includes at least one queue receives the memory requests from the circuitry at the first clock rate and outputs such memory requests at a second clock rate. A memory system stores and retrieves data in response to the memory requests, the memory system outputting data in response to read requests received from input queuing circuitry. An output queue is provided which receives data output from memory at the second clock rate and outputs such data at the first clock rate. Queuing control circuitry is provided which prevents overflow of output queue by controlling the number of memory requests sent in bursts from the input queuing system to the memory system and by controlling the wait time between such bursts.