Patents by Inventor Richard W. Arnold

Richard W. Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10515069
    Abstract: A computer-implemented method of obtaining data of interest from a larger set of data that has been indexed is provided, the method comprising defining, via a user interface of a computing device, a set of attributes associated with a concept. Each attribute associated with the concept is mapped to attributes associated with indexed data, and data of interest relevant to the concept is retrieved based upon the mapping of attributes associated with the concept to attributes associated with the indexed data.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: December 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard W. Arnold, Thomas P. Bishop, Olushola O. Esho, Jordan R. McCoy
  • Patent number: 10445310
    Abstract: A computer-implemented method of obtaining data of interest from a larger set of data that has been indexed is provided, the method comprising defining, via a user interface of a computing device, a set of attributes associated with a concept. Each attribute associated with the concept is mapped to attributes associated with indexed data, and data of interest relevant to the concept is retrieved based upon the mapping of attributes associated with the concept to attributes associated with the indexed data.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard W. Arnold, Thomas P. Bishop, Olushola O. Esho, Jordan R. McCoy
  • Publication number: 20150278286
    Abstract: A computer-implemented method of obtaining data of interest from a larger set of data that has been indexed is provided, the method comprising defining, via a user interface of a computing device, a set of attributes associated with a concept. Each attribute associated with the concept is mapped to attributes associated with indexed data, and data of interest relevant to the concept is retrieved based upon the mapping of attributes associated with the concept to attributes associated with the indexed data.
    Type: Application
    Filed: February 26, 2015
    Publication date: October 1, 2015
    Inventors: Richard W. Arnold, Thomas P. Bishop, Olushola O. Esho, Jordan R. McCoy
  • Publication number: 20150052162
    Abstract: A computer-implemented method of obtaining data of interest from a larger set of data that has been indexed is provided, the method comprising defining, via a user interface of a computing device, a set of attributes associated with a concept. Each attribute associated with the concept is mapped to attributes associated with indexed data, and data of interest relevant to the concept is retrieved based upon the mapping of attributes associated with the concept to attributes associated with the indexed data.
    Type: Application
    Filed: April 1, 2014
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Richard W. Arnold, Thomas P. Bishop, Olushola O. Esho, Jordan R. McCoy
  • Patent number: 7898275
    Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Daniel W. Prevedel, Donald E. Riley, Lester L. Wilson
  • Publication number: 20090039524
    Abstract: Methods and apparatus to support an overhanging region of stacked die are disclosed. A disclosed method comprises bonding a first die onto a substrate, placing a support element on the substrate; and bonding a second die onto the first die, wherein the second die overhangs at least one edge of the first die and the support element is positioned to limit bending of the second die.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles A. Odegard, Richard W. Arnold, Marvin W. Cowens
  • Patent number: 7122895
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Patent number: 7026833
    Abstract: A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding contact elements for electrically contacting one or more chips of a wafer positioned atop a layer of compliant material, and arrayed in a pattern corresponding to a chip pads, a series of conductive vias through the electrically insulating interposer which connect the chip contact elements with an arrangement of leads terminating in a universal arrangement of connectors on the second surface, and a probe card with connectors mating to those on the interposer. The connectors on the interposer is secured are secured to those on the probe card, thereby providing a vertical probe assemblage which makes use of ultrasonic energy to minimize scrub or over travel. The universal probe card is specific to a tester configuration and common to a family of circuits to be tested.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: April 11, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Reynaldo M. Rincon, Richard W. Arnold
  • Patent number: 6970005
    Abstract: A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding contact elements for electrically contacting one or more chips of a wafer positioned atop a layer of compliant material, and arrayed in a pattern corresponding to a chip pads, a series of conductive vias through the electrically insulating interposer which connect the chip contact elements with an arrangement of leads terminating in a universal arrangement of connectors on the second surface, and a probe card with connectors mating to those on the interposer. The connectors on the interposer is secured are secured to those on the probe card, thereby providing a vertical probe assemblage which makes use of ultrasonic energy to minimize scrub or over travel. The universal probe card is specific to a tester configuration and common to a family of circuits to be tested.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: November 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Reynaldo M. Rincon, Richard W. Arnold
  • Patent number: 6906539
    Abstract: A probe card apparatus comprising a rigid substrate having thermal expansion characteristics near that of silicon, laminated with a flex film having laser patterned leads and contact pads, and contact elements comprising noble metals protruding from two major surfaces, the first mirroring the closely spaced chip pads, and the second aligned to the more generously spaced probe card pads, providing an accurate and reproducible, low cost, rapidly fabricated probe contact device, capable of contacting very high density bond pads in either area array or perimeter locations, of being electrically optimized, and readily maintained.
    Type: Grant
    Filed: July 14, 2001
    Date of Patent: June 14, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Lester Wilson, Reynaldo M. Rincon, Jerry Broz, Richard W. Arnold
  • Publication number: 20040169521
    Abstract: A high density probe card contact apparatus including a support block fitted into an opening in a probe card, and holding a plurality of fine tipped needles extending inward and below an opening in the center of the block. The needle tips are a noble metal integrally connected with a less costly conductive metal which forms the more widely spaced fingers of the needles, and which terminate in contacts to the probe card. Laser etching defines the fine needle pattern in a thin sheet of the two-metal composition which is secured to a polymeric film. The contact apparatus is assembled by positioning one or more sections of the polymer with needles on the support film.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 2, 2004
    Inventors: Reynaldo M. Rincon, Jerry Broz, Lester Wilson, Richard W. Arnold
  • Publication number: 20040152232
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Application
    Filed: May 1, 2001
    Publication date: August 5, 2004
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Patent number: 6720574
    Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: April 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Daniel W. Prevedel, Donald E. Riley, Lester L. Wilson
  • Patent number: 6720780
    Abstract: A high density probe card contact apparatus including a support block fitted into an opening in a probe card, and holding a plurality of fine tipped needles extending inward and below an opening in the center of the block. The needle tips are a noble metal integrally connected with a less costly conductive metal which forms the more widely spaced fingers of the needles, and which terminate in contacts to the probe card. Laser etching defines the fine needle pattern in a thin sheet of the two-metal composition which is secured to a polymeric film. The contact apparatus is assembled by positioning one or more sections of the polymer with needles on the support film.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: April 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Reynaldo M. Rincon, Jerry Broz, Lester Wilson, Richard W. Arnold
  • Patent number: 6636063
    Abstract: A probe card having reliable “micro probe” contacts which include a base and an angled probe tip fabricated as a single unit from a thin sheet of a conductive metal having high tensile and yield strength, and coated with a noble metal. The micro probes are secured into precisely dimensioned, and positioned locations on the card, and are electrically connected to traces on the card. Design of the micro probes includes not only the base and probe tip, but also locking features, a stand-off to prevent over compression, and a necked down stem feature for release from the support strap used in transporting and plating during the manufacturing processes.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: October 21, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, James Forster, Reynaldo M. Rincon, Lester Wilson
  • Publication number: 20030094962
    Abstract: A probe card having multiple planes with continuous metal traces from a high density of small, robust probe contacts to peripheral vias which enable connection to a test head is fabricated using technology from the printed circuit card industry. The card includes a relatively small, centrally located recessed plane having a plurality of probe contacts precisely patterned to mate with chip contacts, an array of continuous conductive traces, the substrate is folded at specific crease locations, and formed upward to a second array of creases at which the substrate is bent to form a raised plane parallel to the first.
    Type: Application
    Filed: November 21, 2001
    Publication date: May 22, 2003
    Inventors: Reynaldo M. Rincon, Richard W. Arnold, Lester Wilson, Scott W. Mitchell
  • Publication number: 20030088975
    Abstract: A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank test membrane having a conductive coating or a matrix of conductive lines formed thereon. Once a die bond pad configuration is known, the test membrane can be configured for the die bond pads by using a laser under software control to define connection pads correlating to the die bond pads and also to define interconnecting conductive traces from the connecting pads to contact pads that can be connected to test equipment. In one embodiment, the laser operates to ablate a continuous conductive coating, so as to form conductive pads and traces. In another embodiment, the laser is used to cut various lines in a matrix of conductive lines, so as to define conductive paths from the bond pads to the contact pads for connection to the test equipment.
    Type: Application
    Filed: December 30, 2002
    Publication date: May 15, 2003
    Inventors: Richard W. Arnold, Lester Wilson, James Forster
  • Patent number: 6553661
    Abstract: A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank test membrane having a conductive coating or a matrix of conductive lines formed thereon. Once a die bond pad configuration is known, the test membrane can be configured for the die bond pads by using a laser under software control to define connection pads correlating to the die bond pads and also to define interconnecting conductive traces from the connecting pads to contact pads that can be connected to test equipment. In one embodiment, the laser operates to ablate a continuous conductive coating, so as to form conductive pads and traces. In another embodiment, the laser is used to cut various lines in a matrix of conductive lines, so as to define conductive paths from the bond pads to the contact pads for connection to the test equipment.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: April 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Lester Wilson, James Forster
  • Publication number: 20030062915
    Abstract: A probe card having reliable “micro probe” contacts which include a base and an angled probe tip fabricated as a single unit from a thin sheet of a conductive metal having high tensile and yield strength, and coated with a noble metal. The micro probes are secured into precisely dimensioned, and positioned locations on the card, and are electrically connected to traces on the card. Design of the micro probes includes not only the base and probe tip, but also locking features, a stand-off to prevent over compression, and a necked down stem feature for release from the support strap used in transporting and plating during the manufacturing processes.
    Type: Application
    Filed: October 2, 2001
    Publication date: April 3, 2003
    Inventors: Richard W. Arnold, James Forster, Reynaldo M. Rincon, Lester Wilson
  • Patent number: 6489673
    Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 3, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Lester L. Wilson, Mahmood A. Siddiqui, James A. Forster