Patents by Inventor Richard W. Cutts, Jr.
Richard W. Cutts, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6870814Abstract: A link extender node is used to extend links between end nodes and/or routing nodes in a system area network. A connection includes a first link, coupling an end or routing node to a local port of a first link extender, a second link coupling the remote ports of first and second link extenders, and a third link coupling the local port of the second link extender to an end or routing node. The link extender includes link exception detection logic and transmits a this link bad command on the link generating the exception and transmits an other link bad command on the link not generating the exception.Type: GrantFiled: October 12, 1999Date of Patent: March 22, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: William P. Bunton, David J. Garcia, John C. Krause, William J. Watson, David A. Brown, Richard W. Cutts, Jr., Melvin Kent Benedict
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Patent number: 6263452Abstract: A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: January 8, 1999Date of Patent: July 17, 2001Assignee: Compaq Computer CorporationInventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, Krayn W. Fey, Jr., John Posdro, Kenneth C. Debacker, Nikhil A. Mehta
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Patent number: 6157967Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: December 30, 1997Date of Patent: December 5, 2000Assignee: Tandem Computer IncorporatedInventors: Robert W. Horst, William Edward Baker, Linda Ellen Zalzala, William Patterson Bunton, Richard W. Cutts, Jr., David J. Garcia, John C. Krause, Stephen G. Low, David Paul Sonnier, William Joel Watson, Patracia L. Whiteside
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Patent number: 6073251Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: June 9, 1997Date of Patent: June 6, 2000Assignee: Compaq Computer CorporationInventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Krayn W. Fey, Jr., John Posdro, Kenneth C. DeBacker, Nikhil A. Mehta
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Patent number: 5964835Abstract: A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: October 12, 1999Assignee: Tandem Computers IncorporatedInventors: Daniel L. Fowler, William Edward Baker, William Patterson Bunton, Gary F. Campbell, Richard W. Cutts, Jr., David J. Garcia, Paul N. Hintikka, Robert W. Horst, Geoffrey I. Iswandhi, David P. Sonnier, William Joel Watson, Frank A. Williams
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Patent number: 5890003Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.Type: GrantFiled: September 7, 1993Date of Patent: March 30, 1999Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Kenneth C. Debacker, Robert W. Horst, Nikhil A. Mehta, Douglas E. Jewett, John David Allison, Richard A. Southworth
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Patent number: 5751932Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Tandem Computers IncorporatedInventors: Robert W. Horst, William Edward Baker, Randall G. Banton, John Michael Brown, William F. Bruckert, William Patterson Bunton, Gary F. Campbell, John Deane Coddington, Richard W. Cutts, Jr., Barry Lee Drexler, Harry Frank Elrod, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Geoffrey I. Iswandhi, Douglas Eugene Jewett, Curtis Willard Jones, Jr., James Stevens Klecka, John C. Krause, Stephen G. Low, Susan Stone Meredith, Steven C. Meyers, David P. Sonnier, William Joel Watson, Patricia L. Whiteside, Frank A. Williams, Linda Ellen Zalzala
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Patent number: 5588111Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.Type: GrantFiled: January 31, 1995Date of Patent: December 24, 1996Assignee: Tandem Computers, IncorporatedInventors: Richard W. Cutts, Jr., Randall G. Banton, Douglas E. Jewett
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Patent number: 5574849Abstract: Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.Type: GrantFiled: June 7, 1995Date of Patent: November 12, 1996Assignee: Tandem Computers IncorporatedInventors: David P. Sonnier, Wiliam P. Bunton, Richard W. Cutts, Jr., James S. Klecka, John C. Krause, William J. Watson, Linda E. Zalzala
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Patent number: 5295258Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: January 5, 1990Date of Patent: March 15, 1994Assignee: Tandem Computers IncorporatedInventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Kyran W. Fey, Jr., John Pozdro, Kenneth C. Debacker, Nikhil A. Mehta
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Patent number: 5276823Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.Type: GrantFiled: March 5, 1991Date of Patent: January 4, 1994Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Randall G. Banton, Douglas E. Jewett
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Patent number: 5193175Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.Type: GrantFiled: March 6, 1991Date of Patent: March 9, 1993Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Peter C. Norwood, Kenneth C. DeBacker, Nikhil A. Mehta, Douglas E. Jewett, John D. Allison, Robert W. Horst
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Patent number: 4965717Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.Type: GrantFiled: December 13, 1988Date of Patent: October 23, 1990Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Nikhil A. Mehta, Douglas E. Jewett