Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.

Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.

Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2? radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e.

Abstract: A phase to digital conversion circuit with improved resolution for a rotary traveling wave oscillator. The phase to digital conversion circuit connects with a closed loop transmission line via a plurality of signal lines or nodes distributed along the transmission line. As an oscillating signal propagates around the transmission line, a time waveform of the signal at each of the plurality of signal lines is transmitted to a corresponding plurality of latches. Upon a triggering condition, the plurality of latches simultaneously samples the signals from the plurality of signal lines. At least two reference clock signals are switchably coupled with the plurality of latches latch for triggering the plurality of latches based on an edge transition in each of the reference clock signals compared with an edge transition in each of the signals from the plurality of taps.

Abstract: A phase to digital conversion circuit with improved resolution for a rotary traveling wave oscillator. The phase to digital conversion circuit connects with a closed loop transmission line via a plurality of signal lines or nodes distributed along the transmission line. As an oscillating signal propagates around the transmission line, a time waveform of the signal at each of the plurality of signal lines is transmitted to a corresponding plurality of latches. Upon a triggering condition, the plurality of latches simultaneously samples the signals from the plurality of signal lines. At least two reference clock signals are switchably coupled with the plurality of latches latch for triggering the plurality of latches based on an edge transition in each of the reference clock signals compared with an edge transition in each of the signals from the plurality of taps.

Abstract: An automatically calibrating time to digital conversion circuit. The circuit includes a first circuit node for switchably receiving a first calibration signal and a second circuit node coupled with the first circuit node via a first delay path. A third circuit node for switchably receiving a second calibration signal the same as the first calibration signal is coupled with a fourth circuit node via a second delay path. A calibration portion has a third delay path switchably connected with the fourth circuit node and a fourth delay path switchably connected with the second circuit node. The calibration portion generates a delay adjustment signal for adjusting a time delay of the first delay path such that the first time delay combined with the fourth time delay equals the second time delay combined with the third time delay. The calibration portion is disconnected when calibration is not desired for conserving power.

Abstract: The digital RF transmitter includes a decoder for receiving the in phase (I) and quadrature (Q) digital baseband signals, a phase generator for generating eight waveforms at a carrier frequency where each phase is a multiple of 45 degrees, a first set of main amplifiers of fixed output power, a second set of auxiliary amplifiers of fixed output power such that the ratio of the voltage amplitudes at the outputs of the second set of auxiliary amplifiers to the voltage amplitudes at the outputs of the first set of main amplifiers is fixed at sqrt(2)?1, and a set of multiplexers for selecting one of the eight carrier waveforms, or an off signal, to transmit to each of the first set of main amplifiers and the second set of auxiliary amplifiers based on both the in phase (I) digital baseband signal and the quadrature (Q) digital baseband signal.

Abstract: A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

Abstract: Methods and apparatus for conditioning communications signals based on detection of high-frequency in the polar domain. High-frequency events detected in a phase-difference component of a complex baseband signal in the polar domain are detected and used as a basis for performing hole-blowing on the complex baseband signal in the quadrature domain and/or nonlinear filtering either or both the magnitude and phase-difference components in the polar domain. Alternatively, high-frequency events detected in the phase-difference signal that correlate in time with low-magnitude events detected in a magnitude component of the complex baseband signal are used as a basis for performing hole-blowing on the complex baseband signal in the quadrature domain and/or nonlinear filtering either or both the magnitude and phase-difference components in the polar domain.

Abstract: A relationship is established between measurable characteristics of the DC power input to a power amplifier and the RF output power level. A power circuit is configured to measure the input supply current to the power amplifier and to utilize the relationship between the input supply current and the applied input supply voltage to the output power level, thereby normalizing the output power of an amplified communication signal.

Abstract: The digital RF transmitter includes a decoder for receiving the in phase (I) and quadrature (Q) digital baseband signals, a phase generator for generating eight waveforms at a carrier frequency where each phase is a multiple of 45 degrees, a first set of main amplifiers of fixed output power, a second set of auxiliary amplifiers of fixed output power such that the ratio of the voltage amplitudes at the outputs of the second set of auxiliary amplifiers to the voltage amplitudes at the outputs of the first set of main amplifiers is fixed at sqrt(2)?1, and a set of multiplexers for selecting one of the eight carrier waveforms, or an off signal, to transmit to each of the first set of main amplifiers and the second set of auxiliary amplifiers based on both the in phase (I) digital baseband signal and the quadrature (Q) digital baseband signal.

Abstract: A pulse amplitude modulation (PAM) signal generator that injects a copy of a pulse into the PAM baseband signal prior to frequency upconversion and power amplification. The pulse comprises a function of, or an extra copy of, a pulse in the PAM baseband signal. The pulse injector analyzes the PAM baseband signal for times when a predetermined threshold is exceeded and forms a pulse that is constructed and arranged to reduce the amplitude of the PAM baseband signal to a desired peak amplitude when the pulse is added to the PAM baseband signal. In other embodiments the peak-to-RMS amplitude ratio reducing methods and apparatus used to process PAM signal are adapted for reducing peak-to-RMS amplitude ratios of amplitude modulation signals in polar modulation transmitters. Peak-to-RMS amplitude ratio reduction is performed in the quadrature domain, the polar domain, or both the quadrature and polar domains.

Abstract: The disclosed embodiments provide method and apparatus for digital to analog conversion of a signal that may be limited to a bandpass frequency. In an exemplary embodiment, a bandpass DAC is disclosed which includes a plurality of gates. Each gate receives a carrier signal and one of a plurality of input bits of a digital data. A combiner network is provided which includes a plurality of lossless elements corresponding to each of the plurality of gates. The combiner network receives the gate outputs and provides a digitally weighted signal. A resonating element connected to the combiner network resonates the combiner network and provides a filtered output signal which is linearly combined.

Abstract: A communications transmitter having a main transmit chain for main signal features and one or more auxiliary transmit chains for auxiliary signal enhancements. In one embodiment, a communications signal is produced by digitally processing a representation of a desired signal so as to limit a trajectory of a signal represented by a resulting processed signal. A digital representation of a difference signal approximating a difference between the processed signal and the desired signal is produced. A first modulated, amplified signal is produced in dependence on the processed signal, and a second modulated, amplified signal is produced in response to the difference signal. The first modulated, amplified signal and the second modulated, amplified signal are combined to produce the desired signal. In this manner, a main transmit chain may be optimized with respect to other properties than signal quality (e.g.

Abstract: The disclosed embodiments provide method and apparatus for digital to analog conversion of a signal that may be limited to a bandpass frequency. In an exemplary embodiment, a bandpass DAC is disclosed which includes a plurality of gates. Each gate receives a carrier signal and one of a plurality of input bits of a digital data. A combiner network is provided which includes a plurality of lossless elements corresponding to each of the plurality of gates. The combiner network receives the gate outputs and provides a digitally weighted signal. A resonating element connected to the combiner network resonates the combiner network and provides a filtered output signal which is linearly combined.

Abstract: A low cost high-efficiency all-digital transmitter using all-digital power amplifiers (“DPA”) and various mapping techniques to generate an output signal, which substantially reproduces a baseband signal at a carrier frequency. A baseband signal generator generates a baseband signal which is quantized by a signal processor using a quantization map. A DPA control mapper outputs control signals to phase selectors using the quantized signal and a quantization table. Each phase selector receives one of the control signals and outputs a waveform at a carrier frequency with a phase corresponding to the control signals, or an inactive signal. Each DPA in a DPA array has an assigned weight, receives one of the waveforms from the phase selectors, and outputs a power signal according to the weight of the DPA and the phase of the received waveform. The combined power signal substantially reproduces the baseband signal at the carrier frequency.

Abstract: A frequency demodulator comprises a frequency discriminator configured to generate a frequency modulation signal from frequency modulated signal, circuitry for generating a phase modulation signal from the frequency modulation signal, and a click reduction signal processing (CRSP) circuit operable to remove noise enhancements from the phase modulation signal caused by clicks. By first converting the frequency modulation signal to a phase modulation signal, noise enhancements caused by clicks are more readily distinguished from other noise in the phase modulation signal. After the noise enhancements have been removed by the CRSP, the frequency modulation is recovered substantially free of clicks. Removal of the clicks results in an improved output signal-to-noise ratio, thereby advantageously extending the onset of the threshold effect.

Abstract: This invention, generally speaking, modifies pulse amplitude modulated signals to reduce the ratio of average power to minimum power. The signal is modified in such a manner that the signal quality remains acceptable. The signal quality is described in terms of the Power Spectral Density (PSD) and the Error Vector Magnitude (EVM).

Abstract: A frequency demodulator comprises a frequency discriminator configured to generate a frequency modulation signal from frequency modulated signal, circuitry for generating a phase modulation signal from the frequency modulation signal, and a click reduction signal processing (CRSP) circuit operable to remove noise enhancements from the phase modulation signal caused by clicks. By first converting the frequency modulation signal to a phase modulation signal, noise enhancements caused by clicks are more readily distinguished from other noise in the phase modulation signal. After the noise enhancements have been removed by the CRSP, the frequency modulation is recovered substantially free of clicks. Removal of the clicks results in an improved output signal-to-noise ratio, thereby advantageously extending the onset of the threshold effect.

Abstract: A pulse amplitude modulation (PAM) signal generator that injects a copy of a pulse into the PAM baseband signal prior to frequency upconversion and power amplification. The pulse comprises a function of, or an extra copy of, a pulse in the PAM baseband signal. The pulse injector analyzes the PAM baseband signal for times when a predetermined threshold is exceeded and forms a pulse that is constructed and arranged to reduce the amplitude of the PAM baseband signal to a desired peak amplitude when the pulse is added to the PAM baseband signal.