Patents by Inventor Richard W. Doing

Richard W. Doing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9395992
    Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard W. Doing, Ronald Hall, Kevin N. Magill, James O. Tingen, Todd A. Venton
  • Publication number: 20140143521
    Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Richard W. Doing, Ronald Hall, Kevin N. Magill, James O. Tingen, Todd A. Venton
  • Patent number: 8386712
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 8131976
    Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, Jr.
  • Patent number: 7996618
    Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F Robinson, Sumedh W Sathaye, Jeffrey R Summers
  • Publication number: 20110131394
    Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 2, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 7934081
    Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Publication number: 20100262806
    Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, JR.
  • Publication number: 20100262813
    Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Mary D. Brown, Richard W. Doing, Kevin N. Magill, Brian R. Mestan, Wolfram M. Sauer, Balaram Sinharoy, Jeffrey R. Summers, Albert J. Van Norstrand, JR.
  • Patent number: 7779232
    Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Richard W. Doing, Michael O. Klett, Kevin N. Magill, Brian R. Mestan, David Mui, Balaram Sinharoy, Jeffrey R. Summers
  • Patent number: 7711930
    Abstract: A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: James N. Dieffenderfer, Richard W. Doing, Brian M. Stempel, Steven R. Testa, Kenichi Tsuchiya
  • Patent number: 7707396
    Abstract: A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Bradford, Richard W. Doing, Richard J. Eickemeyer, Wael R. El-Essawy, Douglas R. Logan, Balaram Sinharoy, William E. Speght, Lixin Zhang
  • Patent number: 7644233
    Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 7610449
    Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 7558948
    Abstract: A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Bybell, Richard W. Doing, David D. Dukro
  • Publication number: 20090063819
    Abstract: A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Inventors: Richard W. Doing, Michael O. Klett, Kevin N. Magill, Brian R. Mestan, David Mui, Balaram Sinharoy, Jeffrey R. Summers
  • Publication number: 20080250206
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines is provided. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Application
    Filed: May 7, 2008
    Publication date: October 9, 2008
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M.V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Publication number: 20080250205
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
    Type: Application
    Filed: May 7, 2008
    Publication date: October 9, 2008
    Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M VV A. Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Publication number: 20080250207
    Abstract: A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
    Type: Application
    Filed: May 12, 2008
    Publication date: October 9, 2008
    Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M.V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Publication number: 20080235500
    Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).
    Type: Application
    Filed: June 2, 2008
    Publication date: September 25, 2008
    Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M. V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers