Patents by Inventor Richard W. Gregor

Richard W. Gregor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6680542
    Abstract: The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: January 20, 2004
    Assignee: Agere Systems Inc.
    Inventors: Gerald W. Gibson, Richard W. Gregor, Chun-Yung Sung, Daniel J. Vitkavage, Allen Yen
  • Patent number: 6359339
    Abstract: The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: March 19, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard W. Gregor, Isik C. Kizilyalli, Sailesh M. Merchant, Jaseph R. Radosevich, Pradip K. Roy
  • Patent number: 6252270
    Abstract: A programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate composed at least in part of silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric layer wherein the dielectric layer contains a substantial concentration of an isotope of hydrogen.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: June 26, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard W. Gregor, Isik C. Kizilyalli, Ranbir Singh
  • Patent number: 6023093
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The device includes: (1) a substrate composed at least in part of silicon and (2) a film located over the substrate and having a substantial concentration of an isotope of hydrogen located in the film.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: February 8, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Richard W. Gregor, Isik C. Kizilyalli
  • Patent number: 5312781
    Abstract: A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: May 17, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Richard W. Gregor, Chung W. Leung
  • Patent number: 5110756
    Abstract: Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride to oxide thickness in the second local oxidation step and an annealing step.
    Type: Grant
    Filed: July 3, 1991
    Date of Patent: May 5, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Richard W. Gregor, Chung W. Leung