Abstract: A drive through order system having a vehicle detection system that includes at least two sensors, each affixed to an immovable object, a CPU coupled to a computer readable medium containing instructions to process information from the sensors using fuzzy logic and to output an indicator signal reflecting the presence of a vehicle within a volume sensed by the sensors. In some embodiments, a learn mode supports alteration of fuzzy logic processing parameters. In various embodiments, the system is upgradable and sensor types can be changed and/or new sensors added. In some embodiments, fuzzy logic processing information is modified in dependence upon temporal information.

Abstract: A drive through order system having a vehicle detection system that includes at least two sensors, each affixed to an immovable object, a CPU coupled to a computer readable medium containing instructions to process information from the sensors using fuzzy logic and to output an indicator signal reflecting the presence of a vehicle within a volume sensed by the sensors. In some embodiments, a learn mode supports alteration of fuzzy logic processing parameters. In various embodiments, the system is upgradable and sensor types can be changed and/or new sensors added. In some embodiments, fuzzy logic processing information is modified in dependence upon temporal information.

Abstract: The location of a transmitter can be determined by accurately measuring the elapsed time that it takes for a signal to propagate from a transmission source to a plurality of disparate receivers of a known location. By comparing the received transmitted signal to reference signal a range between each receiver and the transmitter can be determined. By intersecting the spheres defined by each range an accurate location of the transmitter can be obtained.

Abstract: The location of a transmitter can be determined by accurately measuring the elapsed time that it takes for a signal to propagate from a transmission source to a plurality of disparate receivers of a known location. By comparing the received transmitted signal to reference signal a range between each receiver and the transmitter can be determined. By intersecting the spheres defined by each range an accurate location of the transmitter can be obtained.

Abstract: An alarm system, including ease of programming of a family or group of interoperating alarm devices via a learn mode that detects new devices and provides reliable accounting of the group via state dumps to an external system. Reliable communications with the external system are provided via a set of protocols. Disabling of the alarm system is prevented, by transmitting a pre-alarm signal prior to expiration of an entry delay, and by verifying communications with an external device, prior to an alarm-triggering event. Multi-priority message code assignment, including error tolerance, employs n-bit codes with maximized error tolerance. Message transmissions include multiple levels of error protection. The group of monitored alarm devices can be easily set up, purchased and activated by a consumer, and do not become permanent fixtures.

Abstract: A modular Galois-field subfield-power integrated inverter-multiplier circuit that may be used to perform Galois-field division over GF(245). The integrated inverter-multiplier circuit combines subfield-power and parallel multiplication and inversion operations performed therein. The circuit is modular, has a relatively low gate count, and is easily pipelined because it does not use random logic. The circuit implements mathematical calculations known as “Galois-field arithmetic” that are required for a variety of digital signaling and processing applications such as Reed-Solomon and Bose-Chaudhuri-Hochquenghem (BCH) error-correction coding systems. Galois-field division is particularly difficult, typically requiring either a great deal of time or highly complex circuits, or both. The circuit uses a unique combination of subfield and power inversion techniques to carry out multiplicative inversion.

Abstract: A modular Galois-field subfield-power integrated inverter-multiplier circuit that may be used to perform Galois-field division over GF(245). The integrated inverter-multiplier circuit combines subfield-power and parallel multiplication and inversion operations performed therein. The circuit is modular, has a relatively low gate count, and is easily pipelined because it does not use random logic. The circuit implements mathematical calculations known as “Galois-field arithmetic” that are required for a variety of digital signaling and processing applications such as Reed-Solomon and BCH error-correction coding systems. Galois-field division is particularly difficult, typically requiring either a great deal of time or highly complex circuits, or both. The circuit uses a unique combination of subfield and power inversion techniques to carry out multiplicative inversion.

Abstract: A decoder having no offset-adjustment factor for use in calculating error values in Reed-Solomon codes having code-generator-polynomial offset. The decoder comprises a generalized Forney algorithm circuit that processes encoded input data to generate decoded output data. The decoder comprises syndrome computation circuitry that computes syndromes derived from the input data, Berlekamp-Massey computational circuitry that converts the syndromes into error-location (lambda) and error-value (omega) polynomials and coefficients, and Chien-Forney circuitry that processes the lambda and omega coefficients to generate error locations and error values. The syndrome computation circuitry processes the encoded input data to generate syndromes. The syndromes are processed by the Berlekamp-Massey computational circuitry to generate the error-location (lambda) and error-value (omega) polynomials and coefficients.

Abstract: A programmable error-correction decoder embodied in an integrated circuit and error correction decoding method that performs high-speed error correction for digital communication channels and digital data storage applications. The decoder carries out error detection and correction for digital data in a variety of data transmission and storage applications. The decoder has three basic modules, including a syndrome computation module, a Berlekamp-Massey computation module, and a Chien-Forney module. The syndrome computation module calculates syndromes which are intermediate values required to find error locations and values. The Berlekamp-Massey module implements a Berlekamp-Massey algorithm that converts the syndromes to intermediate results known as lambda (&Lgr;) and omega (&OHgr;) polynomials. The Chien-Forney module uses modified Chien-search and Forney algorithms to calculate actual error locations and error values.

Abstract: The present invention uses an acoustic modem embedded in a remote device enhanced with automatic repeat request and forward error correction routines to provide reliable transfer of electronic messages from the messaging server to the remote device. This may provide significantly better error correction than standard PC modems. Also the present invention, may provide a fast, reliable connection sequence by use of a preamble frame. According to an embodiment of the present invention, a method of communicating messages between a messaging server and a remote device is provided. The method includes a variety of steps such as establishing a connection between the messaging server and the remote communication device by transmitting a preamble frame, exchanging data frames between the remote device and the messaging server, detecting and correcting errors in received frames, and re-transmitting received frames, if errors are uncorrectable.

Abstract: An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Abstract: The present invention uses an acoustic modem embedded in a remote device enhanced with automatic repeat request and forward error correction routines to provide reliable transfer of electronic messages from the messaging server to the remote device. This may provide significantly better error correction than standard PC modems. Also the present invention, may provide a fast, reliable connection sequence by use of a preamble frame. According to an embodiment of the present invention, a method of communicating messages between a messaging server and a remote device is provided. The method includes a variety of steps such as establishing a connection between the messaging server and the remote communication device by transmitting a preamble frame, exchanging data frames between the remote device and the messaging server, detecting and correcting errors in received frames, and re-transmitting received frames, if errors are uncorrectable.

Abstract: A circuit and method includes a global parity symbol in a multi-way interleaved Reed-Solomon code implementation to enhance error-detection capability of the Reed-Solomon code. In one embodiment, the global parity symbol is computed over both the data symbols and the check symbols of the Reed-Solomon code, thereby providing data detection capability for errors occurring in the check symbols.

Abstract: An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Abstract: An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Abstract: An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Abstract: A circuit and method includes a global parity symbol in a multi-way interleaved Reed-Solomon code implementation to enhance error-detection capability of the Reed-Solomon code. In one embodiment, the global parity symbol is computed over both the data symbols and the check symbols of the Reed-Solomon code, thereby providing data detection capability for errors occurring in the check symbols.