Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.

Abstract: A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.

Abstract: An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.

Abstract: A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.

Abstract: A device is provided for passing a member through the wall of a sealed chamber. The member has an outer surface having a portion thereof which is substantially formed of metal. A flange has an opening therein which surrounds and is spaced from the metal portion of the member. A solder member completely fills the space between the flange opening and the metal portion of the member for creating a seal therebetween which is capable of maintaining a high pressure differential between opposite sides of the sealed chamber wall. The member is preferably a flat, multi-conductor electrical cable having thin, flat, copper shielding layers on the top and bottom thereof. The metal portion preferably includes a wedge-shaped copper member which surrounds the electrical cable and is intricately affixed to the shielding layers. The solder member is preferably a solder compound comprising 52 percent indium and 48 percent tin.

Abstract: An electrical cable having a plurality of flat, flexible cable sections. Each section has flat, electrically conductive ground layers on at least the top and bottom surfaces thereof, and a plurality of flat, electrically conductive signal conductors between the ground layers. A plurality of dielectric layers separates the signal conductors from each other and from the ground layers. Each signal conductor includes an exposed surface extending a short distance from the end of the conductor along the length of each section. Adjacent cable sections are positioned relative to each other so that the exposed surfaces of corresponding signal conductors face each other. A plurality of connector assemblies is interposed between adjacent cable sections for electrically conducting the exposed surfaces of the corresponding signal conductors. Retaining means are provided for securing the ends of adjacent cable sections and connector assemblies in electrical contact with each other.