Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: An adjustable equalizer network has a series chain of N all pass amplifier stages driving N+1 scaling circuits connected to a final summing circuit that includes circuitry to adjust the frequency response at M+1 frequency control points to obtain a predetermined ripple free minimum phase shift frequency response over a given frequency range. The scaling circuits have scaling coefficients, of magnitude and sign determined by Fourier analysis and an appropriate truncation function, such that the filter has a pass band representative of M+1 contiguous bands conjointly encompassing the frequency range. Calculation of the scaling coefficients and control of the scaling circuits is accomplished through digital computation and manipulation. Some embodiments may use passive circuits or linear analogue circuits as scaling circuits, controlled manually or by a computing device.

Abstract: A tiny pre-amplifier for a small, low voltage, high impedance signal source, usually an electret microphone, exhibiting near unity gain, has an input cascode stage connected to the microphone and a matched balancing cascode stage; both cascode stages are energized from the same power supply circuit. The two cascode stages supply intermediate signals to the inputs of a differential amplifier to generate an output signal having a greatly reduced noise content, independent of power supply variations. The pre-amplifier is wholly integratable, has low power drain, and fits into the microphone housing.

Abstract: An adjustable equalizer network has a series chain of N all pass amplifier stages driving N+1 scaling circuits connected to a final summing circuit that adjusts the frequency response at M+1 frequency control points to obtain a predetermined ripple free minimum phase shift frequency response over a given frequency range. The scaling circuits have scaling coefficients, of magnitude and sign determined by Fourier analysis and an appropriate truncation function, such that the filter has a pass band representative of M+1 contiguous bands conjointly encompassing the frequency range. Calculation of the scaling coefficients and control of the scaling circuits is accomplished through digital computation and manipulation. Some embodiments may use passive circuits or linear analogue circuits as scaling circuits, controlled manually or by a computing device.

Abstract: A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

Abstract: N-parallel bits of data are input to a parallel in-parallel out shift register made of n+m n:1 parallel multiplexers and n-parallel bits of either pure data or combined stuff and data bits are output where, for cycles in which stuff bits are inserted, the non-outputted outputted data bits are recirculated for output on a subsequent cycle followed by newly incoming data bits; such is shown used to advantage in a bit stuffing technique where a synchronous payload envelope pattern may be started at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a selected point after the occurrence of the frame starting signal.

Abstract: An automatic microphone mixer for a multi-microphone audio system in which each microphone audio channel is provided with a control channel including a comparator that compares the microphone output, as an A.C. signal, with a D.C. threshold signal, and that switches the microphone channel to "on" condition when the microphone signal exceeds the threshold; the threshold signal starts at a maximum level for a time T1 and then decreases as a function of time. A D.C. offset is added to the threshold signal in order to prevent low-level extraneous noise sources from activating a channel. All of the control channels are coupled to a threshold signal restoration circuit that drives the threshold signal back to its maximum level each time an audio channel is switched "on." An audio channel that has been switched "on" remains "on" for a time T2 substantially longer than the time T1.

Abstract: A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

Abstract: An adjustable equalizer network comprises a series chain of N all pass amplifier stages driving M minimum phase shift transversal filters connected to a final summing circuit that includes means to adjust each filter output to obtain a ripple free predetermined frequency response over a given frequency range. Each filter includes N+1 scaling circuits connected to an intermediate summing circuit; the scaling circuits have scaling coefficients, of magnitude and sign determined by Fourier analysis and an appropriate truncation function, such that the filter has a pass band representative of one of M contiguous bands conjointly encompassing the frequency range.

Abstract: An audio loudness control system for processing a broad dynamic range of audio input signals (e.g. 70 to 100 dB) comprises a gain-controlled amplifier, a feed forward control signal generator having an audio signal input that develops a feed forward gain control signal having an amplitude representative of long-term input excursions of the audio signal above a predetermined loudness threshold, a feedback control signal generator having an input from the audio output of the amplifier that develops a feedback gain control signal having an amplitude representative of transient output signal excursions above the loudness threshold, and a selector gate that selects the gain control signal of instantaneously higher effective magnitude and applies the selected gain control signal to the gain control input of the amplifier.

Abstract: A priority mixer control for a multi-microphone audio system comprises a threshold signal generator that develops a scanning D.C. threshold signal starting at a maximum level for a time T1 and then decreasing in amplitude as a function of time. Each microphone channel is provided with a control channel including a comparator that compares the microphone signal, as an A.C. signal, with the threshold signal, and that switches the microphone channel to "on" condition when the microphone signal exceeds the threshold; all of the control channels are coupled to a threshold signal restoration means that drives the threshold signal back to its maximum level each time an audio channel is switched "on". An audio channel that has been switched "on" remains "on" for a time T2 substantially longer than the time T1. The number of channels currently in "on" condition is continuously monitored and the output gain is reduced whenever two or more channels are in "on" condition.

Abstract: An audio system comprising a record player, tape deck, microphones, or other signal source which generates stereo signals supplied to two main speakers for reproduction; the stereo signals are added together to afford an intermediate signal which is subjected to at least two successive equal delays to generate a plurality of delayed signals which are summed with the intermediate signal in predetermined amplitude and phase relation to generate a spatial effect signal that is essentially free of noticeable reverberations or echoes. This spatial effect signal is reproduced by a separate speaker in the same listening space as the main speakers to add ambience and diffuseness to the total sound field. In the preferred construction two delayed signals are employed, delay is effected with the signals in digital form, and the summing ratio for the intermediate, first delayed, and second delayed signals is approximately 1:2:1 with the intermediate signal and the second delayed signal in phase opposition.