Abstract: Unauthorized copying of a transaction barcode is prevented by including a sensed condition or other publicly-accessible data with the transaction barcode for use as a comparison with the publicly accessible data determined at a barcode reader. If the sensed condition included in the transaction barcode indicates that the transaction barcode was generated for a different transaction, then the barcode reader invalidates the transaction. For instance, if the barcode was generated too distant in time, position, or sequential transactions, then the barcode reader invalidates the transaction barcode as an unauthorized copy of a transaction barcode generated for a different transaction.

Abstract: An information handling system has a haptic generation module to generate haptic effects including haptic noise and a haptic noise reduction module. The haptic noise reduction module receives characteristics of sound representative of haptic noise generated by a haptic generation module of a device and entering an audio input module of the device, the characteristics including frequencies and timing. It also detects the generation of haptic effects, the generations occurring after the receiving characteristics. It also reduces the effects of haptic noise on digital data representing audio input to the device based upon the received characteristics of the sound. It may reduce the effects by subtracting amplitudes of audio waves representing the haptic noise from amplitudes of audio waves representing the audio input.

Abstract: An information handling system (IHS) includes a processor and a single universal storage device with a system memory region and a mass storage region, wherein disk commands are executed by the processor as transfers between the system memory region and the mass storage region.

Abstract: Systems and methods for providing secure platform services using an information handling system, and which may be implemented to sequester or otherwise isolate sensitive cryptographic processes, as well as the keys used during such decryption and encryption processes. The systems and methods may be implemented as a set of secure services that are available to an operating system or to a Hypervisor executing on an information handling system, and the processing environment may be provided as a closed environment, thus preventing malicious code from infiltrating the processing environment. Dedicated and secure memory space may be employed to prevent key detection through memory scans.

Abstract: Methods and systems are described for factory configuration of existing customer settings so that existing customer settings can be easily configured or pre-configured on new information handling systems. A software module is run on a first information handling system that captures configuration information for an existing information handling system. One example for such configuration information is network configuration information associated with one or more existing wireless and/or wired networks on which a new information handling system will operate. Captured configuration information is transferred to a server information handling system associated with ordering of the new information handling system. The transferred configuration information is then used to configure the new information handling system.

Abstract: A system and method is disclosed for initializing PCI devices in a computer system or information handling system. Upon initialization of the system, each operating system instance of the system attempts to access a PCI bridge device. The first operating system to access the bridge device is granted ownership of the bridge device and the authority to initialize each PCI device coupled to the bridge device. The bridge device assigns each operating system to at least one context included in at least one of the PCI devices. After each of the PCI devices has been initialized, a configuration event is issued with respect to each operating system instance and each assigned PCI device, thereby causing each operating system to recognize each PCI device assigned to each respective operating system instance.

Abstract: A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

Abstract: A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.

Abstract: A better impedance match between a signal transmitting component and a signal transmitting component circuit in a semiconductor circuit is achieved by controlling the parameters of the conducting path coupling the signal transmitting and receiving components. The parameters are controlled such that the portion of the conducting path coupled to the transmitting component has a characteristic impedance generally matching the output impedance of the transmitting component and the portion of the conducting path coupled to the signal receiving component has a characteristic impedance generally matching the input impedance of the signal receiving component. The impedance in portions of the conducting path can controlled by varying the geometric cross-section of the conducting path, the composition of the portion of the conducting path, and/or the amount or nature of the doping of the portion of the conducting path.

Abstract: A computer system including a processor, a main memory and a cache memory uses tagging of various regions of memory to define and select caching properties of transfers between the processor and memory via the cache. The main memory contains not only standard random access memory (RAM) and read-only memory (ROM) but also memory-mapped input/output (I/O) sources. Tagging of the memory regions configures the regions for association with a particular set of caching properties. For example, a memory-mapped video I/O buffer may be tagged with a MM.sub.-- IO.sub.-- VBUF tag designating the caching properties of write-back cacheability with weak read/write ordering. Low-level operating system software, such as the Hardware Abstraction Language (HAL) interface of the Windows NT.TM. operating system or device driver software, initialize the memory regions, the cache and make symbolic associations between the memory regions and the cache.